OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 25

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
4.5.17 UART1 clock divider register
4.5.18 RTC clock divider register
4.5.19 CLKOUT clock source select register
Table 23.
This register configures the UART1 peripheral clock UART1_PCLK. The UART1_PCLK
can be shut down by setting the DIV bits to 0x0.
Remark: Note that the UART1 pins must be configured in the IOCON block before the
UART1 clock can be enabled.
Table 24.
This register configures the RTC peripheral clock RTC_PCLK. The RTC_PCLK can be
shut down by setting the DIV bits to 0x0.
Table 25.
This register configures the clkout_clk signal to be output on the CLKOUT pin. All three
oscillators and the main clock can be selected for the clkout_clk clock.
The CLKOUTCLKUEN register (see
for the update to take effect.
Bit
7:0
31:8
Bit
7:0
31:8
Bit
7:0
31:8
Symbol
DIV
-
Symbol
DIV
-
Symbol
DIV
-
UART0 clock divider register (UART0CLKDIV, address 0x4004 8098) bit
description
UART1 clock divider register (UART1CLKDIV, address 0x4004 809C) bit
description
RTC clock divider register (RTCCLKDIV, address 0x4004 80A0) bit description
All information provided in this document is subject to legal disclaimers.
Description
UART0_PCLK clock divider values
0: Disable UART0_PCLK.
1: Divide by 1.
to
255: Divide by 255.
Reserved
Description
UART1_PCLK clock divider values
0: Disable UART1_PCLK.
1: Divide by 1.
to
255: Divide by 255.
Reserved
Description
RTC_PCLK clock divider values
0: Disable RTC_PCLK.
1: Divide by 1.
to
255: Divide by 255.
Reserved
Rev. 1.1 — 10 March 2011
Section
Chapter 4: LPC122x System control (SYSCON)
4.5.20) must be toggled from LOW to HIGH
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
0
0x00
Reset value
0
0x00
Reset value
0
0x00
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