OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 439

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
20.5.5.5
20.5.5.6
20.5.5.7
20.5.5.8
20.5.5.9
20.6
20.6.1
20.7
20.7.1
20.7.2
20.7.3
20.7.4
20.7.5
20.7.6
20.7.7
20.7.8
20.7.9
20.7.10
Chapter 21: LPC122x General purpose micro DMA controller
21.1
21.2
21.3
21.4
21.4.1
21.4.2
21.5
21.6
21.6.1
21.6.2
21.6.3
21.6.4
21.6.5
21.6.6
21.6.7
21.6.8
21.6.9
21.6.10
21.6.11
Chapter 22: LPC122x CRC engine
22.1
22.2
22.3
22.4
22.5
22.5.1
UM10441
User manual
Code Read Protection (CRP) . . . . . . . . . . . . 307
ISP commands . . . . . . . . . . . . . . . . . . . . . . . . 310
How to read this chapter . . . . . . . . . . . . . . . . 325
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Clocking and power control . . . . . . . . . . . . . 327
Register description . . . . . . . . . . . . . . . . . . . 328
How to read this chapter . . . . . . . . . . . . . . . . 348
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Register description . . . . . . . . . . . . . . . . . . . 349
ISP command abort . . . . . . . . . . . . . . . . . . . 307
Interrupts during ISP. . . . . . . . . . . . . . . . . . . 307
Interrupts during IAP. . . . . . . . . . . . . . . . . . . 307
RAM used by ISP command handler . . . . . . 307
RAM used by IAP command handler . . . . . . 307
ISP entry protection . . . . . . . . . . . . . . . . . . . 309
Unlock <Unlock code> . . . . . . . . . . . . . . . . . 310
Set Baud Rate <Baud Rate> <stop bit> . . . . 311
Echo <setting> . . . . . . . . . . . . . . . . . . . . . . . 311
Write to RAM <start address>
<number of bytes> . . . . . . . . . . . . . . . . . . . . 311
Read Memory <address> <no. of bytes> . . . 312
Prepare sector(s) for write operation <start sector
number> <end sector number> . . . . . . . . . . 312
Copy RAM to flash <Flash address> <RAM
address> <no of bytes> . . . . . . . . . . . . . . . . 313
Go <address> <mode>. . . . . . . . . . . . . . . . . 314
Erase sector(s) <start sector number> <end
sector number>. . . . . . . . . . . . . . . . . . . . . . . 314
Blank check sector(s) <sector number> <end
sector number>. . . . . . . . . . . . . . . . . . . . . . . 315
Memory regions accessible by the micro DMA
controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
DMA system connections . . . . . . . . . . . . . . . 327
DMA status register . . . . . . . . . . . . . . . . . . . 328
DMA configuration register . . . . . . . . . . . . . . 329
Channel control base pointer register. . . . . . 330
Channel alternate control base pointer
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Channel wait on request status register . . . . 330
Channel software request register . . . . . . . . 330
Channel useburst set register. . . . . . . . . . . . 331
Channel useburst clear register . . . . . . . . . . 331
Channel request mask set register . . . . . . . . 332
Channel request mask clear register . . . . . . 332
Channel enable set register . . . . . . . . . . . . . 333
CRC mode register . . . . . . . . . . . . . . . . . . . . 350
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
20.7.11
20.7.12
20.7.13
20.7.14
20.7.15
20.8
20.8.1
20.8.2
20.8.3
20.8.4
20.8.5
20.8.6
20.8.7
20.8.8
20.8.9
20.8.10
20.8.11
20.8.12
20.9
21.6.12
21.6.13
21.6.14
21.6.15
21.6.16
21.6.17
21.6.18
21.6.19
21.6.20
21.7
21.7.1
21.7.2
21.7.3
21.7.4
21.7.4.1
21.7.4.2
21.7.4.3
21.7.4.4
21.7.5
21.7.5.1
21.7.5.2
21.7.5.3
22.5.2
22.5.3
22.5.4
22.6
IAP commands . . . . . . . . . . . . . . . . . . . . . . . 317
Serial Wire Debug (SWD) flash programming
interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Functional description . . . . . . . . . . . . . . . . . 338
Functional description . . . . . . . . . . . . . . . . . 351
Read Part Identification number . . . . . . . . . 315
Read Boot code version number . . . . . . . . . 316
Compare <address1> <address2>
<no of bytes> . . . . . . . . . . . . . . . . . . . . . . . . 316
ReadUID . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
ISP Return Codes . . . . . . . . . . . . . . . . . . . . 317
Prepare sector(s) for write operation . . . . . . 319
Copy RAM to flash . . . . . . . . . . . . . . . . . . . . 320
Erase Sector(s) . . . . . . . . . . . . . . . . . . . . . . 321
Blank check sector(s). . . . . . . . . . . . . . . . . . 321
Read Part Identification number . . . . . . . . . 321
Read Boot code version number . . . . . . . . . 322
Compare <address1> <address2>
<no of bytes> . . . . . . . . . . . . . . . . . . . . . . . . 322
Reinvoke ISP . . . . . . . . . . . . . . . . . . . . . . . . 322
ReadUID . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Erase page. . . . . . . . . . . . . . . . . . . . . . . . . . 323
Erase info page . . . . . . . . . . . . . . . . . . . . . . 323
IAP Status Codes . . . . . . . . . . . . . . . . . . . . . 324
Channel enable clear register . . . . . . . . . . . 333
Channel primary-alternate set register. . . . . 334
Channel primary-alternate clear register . . . 335
Channel priority set register . . . . . . . . . . . . . 335
Channel priority clear register . . . . . . . . . . . 336
Bus error clear register . . . . . . . . . . . . . . . . 336
Channel DMA interrupt status register . . . . . 337
DMA error interrupt enable register . . . . . . . 337
Channel DMA interrupt enable register . . . . 338
DMA control signals . . . . . . . . . . . . . . . . . . . 338
DMA arbitration . . . . . . . . . . . . . . . . . . . . . . 339
DMA priority . . . . . . . . . . . . . . . . . . . . . . . . . 339
DMA cycle types . . . . . . . . . . . . . . . . . . . . . 340
Invalid cycle . . . . . . . . . . . . . . . . . . . . . . . . . 340
Basic cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Auto-request cycle . . . . . . . . . . . . . . . . . . . . 341
Ping-pong cycle . . . . . . . . . . . . . . . . . . . . . . 341
DMA control . . . . . . . . . . . . . . . . . . . . . . . . 342
Source data end pointer. . . . . . . . . . . . . . . . 343
Destination data end pointer . . . . . . . . . . . . 343
Control data configuration . . . . . . . . . . . . . . 344
CRC seed register . . . . . . . . . . . . . . . . . . . . 350
CRC checksum register . . . . . . . . . . . . . . . . 350
CRC data register . . . . . . . . . . . . . . . . . . . . 350
CRC-CCITT set-up . . . . . . . . . . . . . . . . . . . . 351
CRC-16 set-up . . . . . . . . . . . . . . . . . . . . . . . . 351
CRC-32 set-up . . . . . . . . . . . . . . . . . . . . . . . . 351
Chapter 26: Supplementary information
UM10441
© NXP B.V. 2011. All rights reserved.
439 of 442