MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 95

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.4.6 Periodic Interrupt Timer
MC68336/376
USER’S MANUAL
EXTAL
OSCILLATOR
Figure 5-7 is a block diagram of the watchdog timer and the clock control for the pe-
riodic interrupt timer.
The periodic interrupt timer (PIT) allows the generation of interrupts of specific priority
at predetermined intervals. This capability is often used to schedule control system
tasks that must be performed within time constraints. The timer consists of a prescaler,
a modulus counter, and registers that determine interrupt timing, priority and vector as-
signment. Refer to 4.9 Exception Processing for more information.
The periodic interrupt timer modulus counter is clocked by one of two signals. When
the PLL is enabled (MODCLK = 1 during reset), f
disabled (MODCLK = 0 during reset), f
caler (PTP) bit in the periodic interrupt timer register (PITR) determines system clock
prescaling for the periodic interrupt timer. One of two options, either no prescaling, or
prescaling by a factor of 512, can be selected. The value of PTP is affected by the state
of the MODCLK pin during reset, as shown in Table 5-7. System software can change
PTP value.
CRYSTAL
XTAL
Figure 5-7 Periodic Interrupt Timer and Software Watchdog Timer
128
WATCHDOG
SOFTWARE
LPSTOP
RESET
Table 5-7 MODCLK Pin and PTP Bit at Reset
SWT1
SWT0
SWE
FREEZE
CLOCK SELECT
AND DISABLE
0 (PLL disabled)
1 (PLL enabled)
SYSTEM INTEGRATION MODULE
MODCLK
MODCLK
SOFTWARE WATCHDOG TIMER
(2
15
DIVIDER CHAIN — 4 TAPS)
ref
2
9
is used. The value of the periodic timer pres-
PRESCALER
SWSR
1 ( 512)
0 ( 1)
PTP
ref
128 is used. When the PLL is
PERIODIC INTERRUPT TIMER
(8-BIT MODULUS COUNTER)
PICR
SELECT
CLOCK
4
PITR
PIT WATCHDOG BLOCK
SWP
PTP
MOTOROLA
INTERRUPT
PIT
5-17