MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 391

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

D.8 Time Processor Unit (TPU)
D.8.1 TPU Module Configuration Register
TPUMCR — TPU Module Configuration Register
STOP — Low-Power Stop Mode Enable
MC68336/376
USER’S MANUAL
STOP
15
0
RESET:
Table D-51 shows the TPU address map. The column labeled “Access” indicates the
privilege level at which the CPU32 must be operating to access the register. A
designation of “S” indicates that supervisor mode is required. A designation of “S/U”
indicates that the register can be programmed for either supervisor mode access or
unrestricted access.
NOTES:
Access
0 = Enable TPU clocks.
1 = Disable TPU clocks.
14
TCR1P[1:0]
0
S/U
S/U
S/U
S/U
1. Y = M111, where M represents the logic state of the module mapping (MM) bit in the SIMCR.
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
13
0
Address
$YFFE0A
$YFFE0C
$YFFE0E
$YFFE1A
$YFFE1C
$YFFE1E
$YFFE00
$YFFE02
$YFFE04
$YFFE06
$YFFE08
$YFFE10
$YFFE12
$YFFE14
$YFFE16
$YFFE18
$YFFE20
$YFFE22
$YFFE24
$YFFE26
12
TCR2P[1:0]
0
1
11
0
15
Table D-51 TPU Register Map
EMU
10
0
T2CG
REGISTER SUMMARY
9
0
Channel Function Selection Register 0 (CFSR0)
Channel Function Selection Register 1 (CFSR1)
Channel Function Selection Register 2 (CFSR2)
Channel Function Selection Register 3 (CFSR3)
Development Support Control Register (DSCR)
Development Support Status Register (DSSR)
Decoded Channel Number Register (DCNR)
TPU Interrupt Configuration Register (TICR)
Host Service Request Register 0 (HSRR0)
Module Configuration Register (TPUMCR)
Host Service Request Register 1 (HSRR1)
Channel Interrupt Enable Register (CIER)
Channel Interrupt Status Register (CISR)
Service Grant Latch Register (SGLR)
STF
Host Sequence Register 0 (HSQR0)
Host Sequence Register 1 (HSQR1)
Channel Priority Register 0 (CPR0)
8
0
Test Configuration Register (TCR)
Channel Priority Register 1 (CPR1)
SUPV
7
1
Link Register (LR)
PSCK
6
0
5
0
0
4
0
0
3
0
2
0
IARB[3:0]
$YFFE00
MOTOROLA
0
1
0
D-73
0
0