MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 249

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.6.1.3 Emulation Control
11.6.1.4 Low-Power Stop Control
11.6.2 Channel Control Registers
11.6.2.1 Channel Interrupt Enable and Status Registers
MC68336/376
USER’S MANUAL
When T2CG is set, the external TCR2 pin functions as a gate of the DIV8 clock (the
TPU system clock divided by eight). In this case, when the external TCR2 pin is low,
the DIV8 clock is blocked, preventing it from incrementing TCR2. When the external
TCR2 pin is high, TCR2 is incremented at the frequency of the DIV8 clock. When
T2CG is cleared, an external clock from the TCR2 pin, which has been synchronized
and fed through a digital filter, increments TCR2.
The TCR2 field in TPUMCR specifies the value of the prescaler: 1, 2, 4, or 8. Channels
using TCR2 have the capability to resolve down to the TPU system clock divided by
eight. Table 11-2 is a summary of prescaler output.
Asserting the EMU bit in TPUMCR places the TPU in emulation mode. In emulation
mode, the TPU executes microinstructions from TPURAM exclusively. Access to the
TPURAM module through the IMB is blocked, and the TPURAM module is dedicated
for use by the TPU. After reset, EMU can be written only once.
If the STOP bit in TPUMCR is set, the TPU shuts down its internal clocks, shutting
down the internal microengine. TCR1 and TCR2 cease to increment and retain the last
value before the stop condition was entered. The TPU asserts the stop flag (STF) in
TPUMCR to indicate that it has stopped.
The channel control and status registers enable the TPU to control channel interrupts,
assign time functions to be executed on a specified channel, or select the mode of op-
eration or the type of host service request for the time function specified. Refer to Ta-
ble 11-4.
The channel interrupt enable register (CIER) allows the CPU32 to enable or disable
the ability of individual TPU channels to request interrupt service. Setting the appro-
priate bit in the register enables a channel to make an interrupt service request; clear-
ing a bit disables the interrupt.
The channel interrupt status register (CISR) contains one interrupt status flag per
channel. Time functions specify via microcode when an interrupt flag is set. Setting a
flag causes the TPU to make an interrupt service request if the corresponding CIER
TCR2 Prescaler
00
01
10
11
Table 11-2 TCR2 Prescaler Control
Divide By
TIME PROCESSOR UNIT
1
2
4
8
Internal Clock
Divided By
16
32
64
8
External Clock
Divided By
1
2
4
8
MOTOROLA
11-15