MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 228

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.8.1 DASM Interrupts
10.8.2 DASM Registers
10.9 Pulse-Width Modulation Submodule (PWMSM)
10-12
MOTOROLA
The DASM can optionally request an interrupt when the FLAG bit in DASMSIC is set.
To enable interrupts, set the IL[2:0] field in DASMSIC to a non-zero value. The CTM4
compares the CPU32 IP mask value to the priority of the requested interrupt designat-
ed by IL[2:0] to determine whether it should contend for arbitration priority. During ar-
bitration, the BIUSM provides the arbitration value specified by IARB[2:0] in BIUMCR
and IARB3 in DASMSIC. If the CTM4 wins arbitration, it responds with a vector num-
ber generated by concatenating VECT[7:6] in BIUMCR and the six low-order bits
specified by the number of the submodule requesting service. Thus, for DASM9 in the
CTM4, the six low-order bits would be nine in decimal, or %001001 in binary.
The DASM contains one status/interrupt/control register and two data registers (A and
B). All unused bits and reserved address locations return zero when read. Writes to
unused bits and reserved address locations have no effect. The CTM4 contains four
DASMs, each with its own set of registers. Refer to D.7.11 DASM Status/Interrupt/
Control Registers, D.7.12 DASM Data Register A, and D.7.13 DASM Data Register
B for information concerning DASM register and bit descriptions.
The PWMSM allows pulse width modulated signals to be generated over a wide range
of frequencies, independently of other CTM4 output signals. The output pulse width
duty cycle can vary from 0% to 100%, with 16 bits of resolution. The minimum pulse
width is twice the MCU system clock period. For example, the minimum pulse width is
95.4 ns when using a 20.97 MHz clock.
The PWMSM is composed of:
The PWMSM includes its own time base counter and does not use the CTM4 time
base buses; however, it does use the prescaled clock signal PCLK1 generated by the
CPSM. Refer to 10.5 Counter Prescaler Submodule (CPSM) and Figure 10-1 for
more information. Figure 10-6 shows a block diagram of the PWMSM.
• An output flip-flop with output polarity control
• Clock prescaler and selection logic
• A 16-bit up-counter
• Two registers to hold the current and next pulse width values
• Two registers to hold the current and next pulse period values
• A pulse width comparator
• A system state sequencer
• Logic to create 0% and 100% pulses
• Interrupt logic
• A status, interrupt and control register
• A submodule bus interface
CONFIGURABLE TIMER MODULE 4
USER’S MANUAL
MC68336/376