MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 358

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

D.6 Queued Serial Module
D.6.1 QSM Configuration Register
QSMCR — QSM Configuration Register
D-40
MOTOROLA
RESET:
STOP
Access
NOTES:
15
0
Table D-31 shows the QSM address map. The column labeled “Access” indicates the
privilege level at which the CPU32 must be operating to access the register. A
designation of “S” indicates that supervisor mode is required. A designation of “S/U”
indicates that the register can be programmed for either supervisor mode access or
unrestricted access.
QSMCR bits enable stop and freeze modes, and determine the arbitration priority of
QSM interrupt requests.
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S
S
S
1. Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
FRZ1
14
0
$YFFC20 –
$YFFD00 –
$YFFD20 –
$YFFD40 –
Address
$YFFC0A
$YFFC0C
$YFFC0E
$YFFC1A
$YFFC1C
$YFFC1E
$YFFCFF
$YFFC00
$YFFC02
$YFFC04
$YFFC06
$YFFC08
$YFFC10
$YFFC12
$YFFC14
$YFFC16
$YFFC18
$YFFD1F
$YFFD3F
$YFFD4F
FRZ0
13
0
1
12
0
0
15
PQS Pin Assignment Register (PQSPAR)
QSM Interrupt Level Register (QILR)
11
0
0
SPI Control Register 3 (SPCR3)
Table D-31 QSM Address Map
10
0
0
REGISTER SUMMARY
Not Used
9
0
0
QSM Module Configuration Register (QSMCR)
8
0
0
SCI Control 0 Register (SCCR0)
SCI Control 1 Register (SCCR1)
SPI Control Register 0 (SPCR0)
SPI Control Register 1 (SPCR1)
SPI Control Register 2 (SPCR2)
QSM Test Register (QTEST)
SCI Status Register (SCSR)
SCI Data Register (SCDR)
Command RAM (CR[0:F])
Transmit RAM (TR[0:F])
Receive RAM (RR[0:F])
SUPV
7
1
Not Used
Not Used
Not Used
Not Used
8 7
6
0
0
PQS Data Direction Register (DDRQS)
QSM Interrupt Vector Register (QIVR)
5
0
0
PQS Data Register (PORTQS)
SPI Status Register (SPSR)
4
0
0
3
0
USER’S MANUAL
2
0
IARB[3:0]
MC68336/376
$YFFC00
1
0
0
0
0