MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 346

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

QADCMCR — Module Configuration Register
D.5 QADC Module
D.5.1 QADC Module Configuration Register
STOP — Low-Power Stop Mode Enable
D-28
RESET:
MOTOROLA
STOP
15
0
Table D-24 shows the QADC address map. The column labeled “Access” indicates
the privilege level at which the CPU32 must be operating to access the register. A des-
ignation of “S” indicates that supervisor mode is required. A designation of “S/U”
indicates that the register can be programmed for either supervisor mode access or
unrestricted access.
When the STOP bit is set, the clock signal to the QADC is disabled, effectively turning
off the analog circuitry.
0 = Enable QADC clock.
1 = Disable QADC clock.
FRZ
14
0
NOTES:
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
1. Y = M111, where M is the logic state of the module mapping (MM) bit in SIMCR.
—
—
—
—
S
S
S
13
$YFF280 – $YFF2AE
$YFF2B0 – $YFF2FE
$YFF380 – $YFF3AE
$YFF3B0 – $YFF3FE
$YFF212 – $YFF22E
$YFF230 – $YFF27E
$YFF300 – $YFF32E
$YFF330 – $YFF37E
12
Address
$YFF20A
$YFF20C
$YFF20E
$YFF200
$YFF202
$YFF204
$YFF206
$YFF208
$YFF210
11
NOT USED
1
10
Table D-24 QADC Address Map
REGISTER SUMMARY
15
9
Port A Data (PORTQA)
8
Right Justified, Unsigned Result Register (RJURR)
Left Justified, Unsigned Result Register (LJURR)
Left Justified, Signed Result Register (LJSRR)
Module Configuration Register (QADCMCR)
Conversion Command Word (CCW) Table
SUPV
7
1
Port Data Direction Register (DDRQA)
Interrupt Register (QADCINT)
Control Register 0 (QACR0)
Control Register 1 (QACR1)
Control Register 2 (QACR2)
Test Register (QADCTEST)
6
Status Register (QASR)
Result Word Table
Result Word Table
Result Word Table
NOT USED
Reserved
Reserved
Reserved
Reserved
8
5
7
4
Port B Data (PORTQB)
3
0
USER’S MANUAL
2
0
IARB[3:0]
MC68336/376
$YFF200
1
0
0
0
0