MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 223

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.6.6 FCSM Registers
10.7 Modulus Counter Submodule (MCSM)
MC68336/376
USER’S MANUAL
arbitration priority. During arbitration, the BIUSM provides the arbitration value speci-
fied by IARB[2:0] in BIUMCR and IARB3 in FCSMSIC. If the CTM4 wins arbitration, it
responds with a vector number generated by concatenating VECT[7:6] in BIUMCR
and the six low-order bits specified by the number of the submodule requesting ser-
vice. Thus, for FCSM12 in CTM4, six low-order bits would be 12 in decimal, or
%001100 in binary.
The FCSM contains a status/interrupt/control register and a counter register. All un-
used bits and reserved address locations return zero when read. Writes to unused bits
and reserved address locations have no effect. Refer to D.7.6 FCSM Status/Inter-
rupt/Control Register and D.7.7 FCSM Counter Register for information concerning
FCSM register and bit descriptions.
The modulus counter submodule (MCSM) is an enhanced FCSM. The MCSM con-
tains a 16-bit modulus latch, a 16-bit loadable up-counter, counter loading logic, a
clock selector, selectable time base bus drivers, and an interrupt interface. A modulus
register provides the added flexibility of recycling the counter at a count other than 64K
clock cycles. The content of the modulus latch is transferred to the counter when an
overflow occurs, or when a user-specified edge transition occurs on a designated
modulus load input pin. In addition, a write to the modulus counter simultaneously
loads both the counter and the modulus latch with the specified value. The counter
then begins incrementing from this new value.
In order to count, the MCSM requires the CPSM clock signals to be present. After re-
set, the MCSM does not count until the prescaler in the CPSM starts running (when
the software sets the PRUN bit). This allows all counters in the CTM4 submodules to
be synchronized.
The CTM4 contains two MCSMs. Figure 10-4 shows a block diagram of the MCSM.
CONFIGURABLE TIMER MODULE 4
MOTOROLA
10-7