MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 392

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

TCR1P[1:0] — Timer Count Register 1 Prescaler Control
TCR2P[1:0] — Timer Count Register 2 Prescaler Control
EMU — Emulation Control
T2CG — TCR2 Clock/Gate Control
D-74
MOTOROLA
TCR1 is clocked from the output of a prescaler. The prescaler's input is the internal
TPU system clock divided by either 4 or 32, depending on the value of the PSCK bit.
The prescaler divides this input by 1, 2, 4, or 8. Channels using TCR1 have the capa-
bility to resolve down to the TPU system clock divided by four. Table D-52 is a sum-
mary of prescaler output.
TCR2 is clocked from the output of a prescaler. If T2CG = 0, the input to the TCR2
prescaler is the external TCR2 clock source. If T2CG = 1, the input is the TPU system
clock divided by eight. The TCR2P field specifies the value of the prescaler: 1, 2, 4, or
8. Channels using TCR2 have the capability to resolve down to the TPU system clock
divided by eight. Table D-53 is a summary of prescaler output.
In emulation mode, the TPU executes microinstructions from TPURAM exclusively.
Access to the TPURAM module via the IMB is blocked, and the TPURAM module is
dedicated for use by the TPU. After reset, this bit can be written only once.
When T2CG is set, the external TCR2 pin functions as a gate of the DIV8 clock (the
TPU system clock divided by eight). In this case, when the external TCR2 pin is low,
the DIV8 clock is blocked, preventing it from incrementing TCR2. When the external
TCR2 pin is high, TCR2 is incremented at the frequency of the DIV8 clock. When
T2CG is cleared, an external clock input from the TCR2 pin, which has been synchro-
nized and fed through a digital filter, increments TCR2.
0 = TPU and TPURAM operate normally.
1 = TPU and TPURAM operate in emulation mode.
0 = TCR2 pin used as clock source for TCR2.
1 = TCR2 pin used as gate of DIV8 clock for TCR2.
TCR2P[1:0]
00
01
10
11
Table D-52 TCR1 Prescaler Control Bits
Table D-53 TCR2 Prescaler Control Bits
TCR1P[1:0]
00
01
10
11
Divide By
Prescaler
REGISTER SUMMARY
1
2
4
8
Prescaler
Divide By
1
2
4
8
Internal Clock
Divided By
PSCK = 0
f
f
f
f
sys
sys
sys
sys
TCR1 Clock Input
16
32
64
8
128
256
32
64
PSCK = 1
f
f
f
f
sys
sys
sys
sys
External Clock
Divided By
16
32
4
8
1
2
4
8
USER’S MANUAL
MC68336/376