MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 325

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

FRZSW — Freeze Software Enable
FRZBM — Freeze Bus Monitor Enable
SHEN[1:0] — Show Cycle Enable
SUPV — Supervisor/Unrestricted Data Space
MM — Module Mapping
IARB[3:0] — Interrupt Arbitration ID
D.2.2 System Integration Test Register
SIMTR — System Integration Test Register
MC68336/376
USER’S MANUAL
The SHEN field determines how the external bus is driven during internal transfer
operations. A show cycle allows internal transfers to be monitored externally.
Table D-4 shows whether show cycle data is driven externally, and whether external
bus arbitration can occur. To prevent bus conflict, external peripherals must not be en-
abled during show cycles.
The SUPV bit places the SIM global registers in either supervisor or user data space.
Each module that can generate interrupts, including the SIM, has an IARB field. Each
IARB field can be assigned a value from $0 to $F. During an interrupt acknowledge
cycle, IARB permits arbitration among simultaneous interrupts of the same priority lev-
el. The reset value of the SIM IARB field is $F. This prevents SIM interrupts from being
discarded during system initialization.
Used for factory test only.
0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer
1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
0 = Registers with access controlled by the SUPV bit are accessible in either
1 = Registers with access controlled by the SUPV bit are restricted to supervisor
0 = Internal modules are addressed from $7FF000 – $7FFFFF.
1 = Internal modules are addressed from $FFF000 – $FFFFFF.
counters continue to run.
counters are disabled, preventing interrupts during background debug mode.
supervisor or user mode.
access only.
SHEN[1:0]
00
01
10
11
Table D-4 Show Cycle Enable Bits
Show cycles disabled, external arbitration enabled
Show cycles enabled, external arbitration disabled
Show cycles enabled, external arbitration enabled
Show cycles enabled, external arbitration enabled;
internal activity is halted by a bus grant
REGISTER SUMMARY
Action
$YFFA02
MOTOROLA
D-7