MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 218

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.2 Address Map
10.3 Time Base Bus System
10-2
MOTOROLA
The time base buses originate in a counter submodule and are used by the action sub-
modules. Two time base buses are accessible to each submodule.
The bus interface unit submodule (BIUSM) allows all the CTM4 submodules to pass
data to and from the IMB via the submodule bus (SMB).
The counter prescaler submodule (CPSM) generates six different clock frequencies
which can be used by any counter submodule. This submodule is contained within the
BIUSM.
The free-running counter submodule (FCSM) has a 16-bit up counter with an associ-
ated clock source selector, selectable time-base bus drivers, writable control registers,
readable status bits, and interrupt logic.The CTM4 has one FCSM.
The modulus counter submodule (MCSM) is an enhanced FCSM. A modulus register
gives the additional flexibility of recycling the counter at a count other than 64K clock
cycles. The CTM4 has two MCSMs.
The double-action submodule (DASM) provides two 16-bit input capture or two 16-bit
output compare functions that can occur automatically without software intervention.
The CTM4 has four DASMs.
The pulse width modulation submodule (PWMSM) can generate pulse width
modulated signals over a wide range of frequencies, independently of other CTM out-
put signals. PWMSMs are not affected by time base bus activity. The CTM4 has four
PWMSMs.
The CTM4 address map occupies 256 bytes from address $YFF400 to $YFF4FF. All
CTM4 registers are accessible only when the CPU32 is in supervisor mode. All re-
served addresses return zero when read, and writes have no effect. Refer to D.7 Con-
figurable Timer Module 4 for information concerning CTM4 address map and
register bit/field descriptions.
The CTM4 time base bus system is composed of three 16-bit buses: TBB1, TBB2, and
TBB4. These buses are used to transfer timing information from the counter submod-
ules to the action submodules. Two time base buses are available to each submodule.
A counter submodule can drive one of the two time base buses to which it is connect-
ed. Each action submodule can choose one of the two time base buses to which it is
connected as its time base. Control bits within each CTM4 submodule select connec-
tion to the appropriate time base bus.
The time base buses are precharge/discharge type buses with wired-OR capability.
Therefore, no hardware damage occurs when more than one counter drives the same
bus at the same time.
CONFIGURABLE TIMER MODULE 4
USER’S MANUAL
MC68336/376