MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 156

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.3.1 QSPI Registers
9.3.1.1 Control Registers
9-6
MOTOROLA
Serial transfers of eight to sixteen can be specified. Programmable transfer length sim-
plifies interfacing to devices that require different data lengths.
An inter-transfer delay of 17 to 8192 system clocks can be specified (default is 17 sys-
tem clocks). Programmable delay simplifies the interface to devices that require differ-
ent delays between transfers.
A dedicated 80-byte RAM is used to store received data, data to be transmitted, and
a queue of commands. The CPU32 can access these locations directly. This allows
serial peripherals to be treated like memory-mapped parallel devices.
The command queue allows the QSPI to perform up to 16 serial transfers without
CPU32 intervention. Each queue entry contains all the information needed by the
QSPI to independently complete one serial transfer.
A pointer identifies the queue location containing the data and command for the next
serial transfer. Normally, the pointer address is incremented after each serial transfer,
but the CPU32 can change the pointer value at any time. Support of multiple-tasks can
be provided by segmenting the queue.
The QSPI has four peripheral chip-select pins. The chip-select signals simplify inter-
facing by reducing CPU32 intervention. If the chip-select signals are externally decod-
ed, 16 independent select signals can be generated.
Wrap-around mode allows continuous execution of queued commands. In wrap-
around mode, newly received data replaces previously received data in the receive
RAM. Wrap-around mode can simplify the interface with A/D converters by continu-
ously updating conversion values stored in the RAM.
Continuous transfer mode allows transfer of an uninterrupted bit stream. Any number
of bits in a range from 8 to 256 can be transferred without CPU32 intervention. Longer
transfers are possible, but minimal intervention is required to prevent loss of data. A
standard delay of 17 system clocks is inserted between the transfer of each queue
entry.
The programmer’s model for the QSPI consists of the QSM global and pin control reg-
isters, four QSPI control registers (SPCR[0:3]), the status register (SPSR), and the 80-
byte QSPI RAM. Registers and RAM can be read and written by the CPU32. Refer to
D.6 Queued Serial Module for register bit and field definitions.
Control registers contain parameters for configuring the QSPI and enabling various
modes of operation. The CPU32 has read and write access to all control registers. The
QSM has read access only to all bits except the SPE bit in SPCR1. Control registers
must be initialized before the QSPI is enabled to insure defined operation. SPCR1
must be written last because it contains the QSPI enable bit (SPE).
Writing a new value to any control register except SPCR2 while the QSPI is enabled
disrupts operation. SPCR2 is buffered. New SPCR2 values become effective after
completion of the current serial transfer. Rewriting NEWQP in SPCR2 causes execu-
QUEUED SERIAL MODULE
USER’S MANUAL
MC68336/376