MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 224

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.7.1 MCSM Modulus Latch
10.7.2 MCSM Counter
10.7.2.1 Loading the MCSM Counter Register
10-8
MOTOROLA
The 16-bit modulus latch is a read/write register that is used to reload the counter au-
tomatically with a predetermined value. The contents of the modulus latch register can
be read at any time. Writing to the register loads the modulus latch with the new value.
This value is then transferred to the counter register when the next load condition
occurs. However, writing to the corresponding counter register loads the modulus
latch and the counter register immediately with the new value. The modulus latch reg-
ister is cleared to $0000 by reset.
The counter is composed of a 16-bit read/write register associated with a 16-bit incre-
menter. Reading the counter transfers the contents of the counter register to the data
bus. Writing to the counter loads the modulus latch and the counter register immedi-
ately with the new value.
The MCSM counter is loaded either by writing to the counter register or by loading it
from the modulus latch when a counter overflow occurs. Counter overflow will set the
COF bit in the MCSM status/interrupt/control register (MCSMSIC).
CONTROL REGISTER BIT
CONTROL REGISTER BIT
LOAD INPUT
MODULUS
INPUT PIN
PIN CTD9
CLOCK
CTM2C
IN2
IN1
6 CLOCKS (PCLK[1:6]) FROM PRESCALER
When the modulus latch is loaded with $FFFF, the overflow flag is set
on every counter clock pulse.
MODULUS LOAD
INPUT PIN CTML
CONTROL REGISTER BITS
DETECT
EDGEN EDGEP
EDGE
DETECT
EDGE
Figure 10-4 MCSM Block Diagram
CONTROL REGISTER BITS
TBBA
CONFIGURABLE TIMER MODULE 4
CLK2
TBBB
CLK1 CLK0
SELECT
CLOCK
SUBMODULE BUS
MODULUS
CONTROL
NOTE
16-BIT UP COUNTER
WRITE
BOTH
SELECT
MODULUS REGISTER
BUS
CONTROL REGISTER BITS
TIME BASE BUSES
COF
DRVA DRVB
OVERFLOW
CONTROL REGISTER BITS
IL2
IL1
IL1
IL0
INTERRUPT
CONTROL
IARB3
USER’S MANUAL
MC68336/376
CTM MCSM BLOCK