MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 382

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MC68376BGMAB20

Manufacturer Part Number
MC68376BGMAB20
Description
IC MCU 32BIT 8K ROM 160-QFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Datasheets

Specifications of MC68376BGMAB20

Core Processor
CPU32
Core Size
32-Bit
Speed
20MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
18
Program Memory Type
ROMless
Ram Size
7.5K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
160-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68376BGMAB20
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
IL[2:0] — Interrupt Level
IARB3 — Interrupt Arbitration Bit 3
WOR — Wired-OR Mode
BSL — Bus Select
IN — Input Pin Status
D-64
MOTOROLA
The FLAG bit is set by hardware and cleared by software, or by system reset. Clear
the FLAG bit either by writing a zero to it, having first read the bit as a one, or by se-
lecting the DIS mode.
When the DASM generates an interrupt request, IL[2:0] determines which of the
interrupt request signals is asserted. When a request is acknowledged, the CTM4
compares IL[2:0] to a mask value supplied by the CPU32 to determine whether to
respond. IL[2:0] must have a value in the range of $0 (interrupts disabled) to $7
(highest priority).
This bit and the IARB[2:0] field in BIUMCR are concatenated to determine the interrupt
arbitration number for the submodule requesting interrupt service. Refer to D.7.1 BIU
Module Configuration Register for more information on IARB[2:0].
In the DIS, IPWM, IPM and IC modes, the WOR bit is not used. Reading this bit returns
the value that was previously written.
In the OCB, OCAB and OPWM modes, the WOR bit selects whether the output buffer
is configured for open-drain or normal operation.
This bit selects the time base bus connected to the DASM.
In the DIS, IPWM, IPM and IC modes, this read-only status bit reflects the logic level
on the input pin.
In the OCB, OCAB and OPWM modes, reading this bit returns the value latched on
the output flip-flop, after EDPOL polarity selection.
Writing to this bit has no effect.
0 = Output buffer operates in normal mode.
1 = Output buffer operates in open-drain mode.
0 = DASM is connected to time base bus A.
1 = DASM is connected to time base bus B.
OPWM
OCAB
Mode
IPWM
OCB
IPM
DIS
IC
FLAG bit is reset
FLAG bit is set each time there is a capture on channel A
FLAG bit is set each time there is a capture on channel A, except for the first time
FLAG bit is set each time there is a capture on channel A
FLAG bit is set each time there is a successful comparison on channel B
FLAG bit is set each time there is a successful comparison on either channel A or B
FLAG bit is set each time there is a successful comparison on channel A
Table D-44 DASM Mode Flag Status Bit States
REGISTER SUMMARY
Flag Status Bit State
USER’S MANUAL
MC68336/376

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