MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 404

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

HALT — Halt TouCAN S-Clock
NOTRDY — TouCAN Not Ready
WAKEMSK — Wakeup Interrupt Mask
SOFTRST — Soft Reset
D-86
MOTOROLA
Setting the HALT bit has the same effect as assertion of the IMB FREEZE signal on
the TouCAN without requiring that FREEZE be asserted.
This bit is set to one after reset. It should be cleared after initializing the message buff-
ers and control registers. TouCAN message buffer receive and transmit functions are
inactive until this bit is cleared.
When HALT is set, the write access to certain registers and bits that are normally read-
only is allowed.
The NOTRDY bit indicates that the TouCAN is either in low-power stop mode or debug
mode.
This bit is read-only and is set only when the TouCAN enters low-power stop mode or
debug mode. It is cleared once the TouCAN exits either mode, either by synchroniza-
tion to the CAN bus or by the self-wake mechanism.
The WAKEMSK bit enables wake-up interrupt requests.
When the SOFTRST bit is asserted, the TouCAN resets its internal state machines
(sequencer, error counters, error flags, and timer) and the host interface registers
(CANMCR, CANICR, CANTCR, IMASK, and IFLAG).
The configuration registers that control the interface with the CAN bus are not changed
(CANCTRL[0:2] and PRESDIV). Message buffers and receive message masks are
also not changed. This allows SOFTRST to be used as a debug feature while the sys-
tem is running.
Setting SOFTRST also clears the STOP bit in CANMCR.
After setting SOFTRST, allow one complete bus cycle to elapse for the internal
TouCAN circuitry to completely reset before executing another access to CANMCR.
This bit is cleared by the TouCAN once the internal reset cycle is completed.
0 = The TouCAN operates normally.
1 = Place TouCAN in debug mode if FRZ = 1.
0 = TouCAN has exited low-power stop mode or debug mode.
1 = TouCAN is in low-power stop mode or debug mode.
0 = Wake up interrupt is disabled.
1 = Wake up interrupt is enabled.
0 = Soft reset cycle completed
1 = Soft reset cycle initiated
REGISTER SUMMARY
USER’S MANUAL
MC68336/376