MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 379

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

MCSM2SIC — MCSM2 Status/Interrupt/Control Register
MCSM11SIC — MCSM11 Status/Interrupt/Control Register
D.7.7 FCSM Counter Register
FCSMCNT — FCSM Counter Register
D.7.8 MCSM Status/Interrupt/Control Registers
COF — Counter Overflow Flag
IL[2:0] — Interrupt Level Field
IARB3 — Interrupt Arbitration Bit 3
DRV[A:B] — Drive Time Base Bus
MC68336/376
USER’S MANUAL
COF
15
15
U
0
RESET:
RESET:
The FCSM counter register is a read/write register. A read returns the current value of
the counter. A write loads the counter with the specified value. The counter then
begins incrementing from this new value.
This bit indicates whether or not a counter overflow has occurred. An overflow of the
MCSM counter is defined as the transition of the counter from $FFFF to $xxxx, where
$xxxx is the value contained in the modulus latch. If the IL[2:0] field is non-zero, an
interrupt request is generated when the COF bit is set.
This flag bit is set only by hardware and cleared only by software or by system reset.
To clear the flag, first read the bit as a one, then write a zero to the bit.
When the MCSM generates an interrupt request, IL[2:0] determines which of the
interrupt request signals is asserted. When a request is acknowledged, the CTM4
compares IL[2:0] to a mask value supplied by the CPU32 to determine whether to
respond. IL[2:0] must have a value in the range of $0 (interrupts disabled) to $7
(highest priority).
This bit and the IARB[2:0] field in BIUMCR are concatenated to determine the interrupt
arbitration number for the submodule requesting interrupt service. Refer to D.7.1 BIU
Module Configuration Register for more information on IARB[2:0].
This field controls the connection of the MCSM to time base buses A and B. Refer to
Table D-41.
0 = Counter overflow has not occurred
1 = Counter overflow has occurred
14
14
0
0
IL[2:0]
13
13
0
0
12
12
0
0
IARB3
11
11
0
0
USED
NOT
10
10
0
0
DRVA
REGISTER SUMMARY
9
0
9
0
DRVB
8
0
8
0
IN2
U
7
7
0
IN1
6
U
6
0
EDGEN EDGEP
5
0
5
0
4
0
4
0
USED
NOT
3
0
3
0
2
0
2
0
MOTOROLA
$YFF462
$YFF410
$YFF458
CLK[2:0]
1
0
1
0
D-61
0
0
0
0