MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 94

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5-16
MOTOROLA
Both writes must occur before time-out in the order listed. Any number of instructions
can be executed between the two writes.
Watchdog clock rate is affected by the software watchdog prescale (SWP) bit and the
software watchdog timing (SWT[1:0]) field in SYPCR.
SWP determines system clock prescaling for the watchdog timer and determines that
one of two options, either no prescaling or prescaling by a factor of 512, can be select-
ed. The value of SWP is affected by the state of the MODCLK pin during reset, as
shown in Table 5-5. System software can change SWP value.
SWT[1:0] selects the divide ratio used to establish the software watchdog time-out
period. The following equation calculates the time-out period for a fast reference fre-
quency.
The following equation calculates the time-out period for an externally input clock
frequency.
Table 5-6 shows the divide ratio for each combination of SWP and SWT[1:0] bits.
When SWT[1:0] are modified, a watchdog service sequence must be performed be-
fore the new time-out period can take effect.
Time-out Period
Time-out Period
SWP
Table 5-5 MODCLK Pin and SWP Bit During Reset
0
0
0
0
1
1
1
1
Table 5-6 Software Watchdog Ratio
=
SYSTEM INTEGRATION MODULE
0 (PLL disabled)
1 (PLL enabled)
------------------------------------------------------------------------------------------------------------------------------------------- -
128 Divide Ratio Specified by SWP and SWT[1:0]
=
MODCLK
----------------------------------------------------------------------------------------------------------------------- -
SWT[1:0]
Divide Ratio Specified by SWP and SWT[1:0]
00
01
10
11
00
01
10
11
1 ( 512)
0 ( 1)
SWP
Watchdog Time-Out Period
f
f
ref
ref
2
2
2
2
2
2
2
2
11
13
15
18
20
22
24
9
f
f
f
f
f
f
f
f
sys
sys
sys
sys
sys
sys
sys
sys
USER’S MANUAL
MC68336/376