MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 111

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

MC68336/376
USER’S MANUAL
BREAKPOINT OPERATION FLOW
IF BREAKPOINT INSTRUCTION EXECUTED AND
IF BKPT PIN ASSERTED AND
IF BERR ASSERTED:
IF BKPT INSTRUCTION EXECUTED:
IF BKPT PIN ASSERTED:
IF BKPT INSTRUCTION EXECUTED:
IF BKPT PIN ASSERTED:
IF BREAKPOINT INSTRUCTION EXECUTED:
IF BKPT PIN ASSERTED:
DSACK IS ASSERTED:
1) PLACE LATCHED DATA IN INSTRUCTION PIPELINE
2) CONTINUE PROCESSING
1) INITIATE ILLEGAL INSTRUCTION PROCESSING
1) INITIATE HARDWARE BREAKPOINT PROCESSING
1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]
4) PLACE BREAKPOINT NUMBER ON ADDR[4:2]
5) CLEAR T-BIT (ADDR1) TO ZERO
6) SET SIZE TO WORD
7) ASSERT AS AND DS
1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]
4) PLACE ALL ONES ON ADDR[4:2]
5) SET T-BIT (ADDR1) TO ONE
6) SET SIZE TO WORD
7) ASSERT AS AND DS
DSACK IS ASSERTED:
1) CONTINUE PROCESSING
1) LATCH DATA
2) NEGATE AS AND DS
3) GO TO (A)
1) NEGATE AS AND DS
2) GO TO (A)
1) NEGATE AS AND DS
2) GO TO (B)
(A)
ACKNOWLEDGE BREAKPOINT
CPU32
Figure 5-13 Breakpoint Operation Flowchart
(B)
SYSTEM INTEGRATION MODULE
IF BKPT INSTRUCTION EXECUTED:
IF BKPT ASSERTED:
1) NEGATE DSACK or BERR
1) PLACE REPLACEMENT OPCODE ON DATA BUS
2) ASSERT DSACK
1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING
1) ASSERT DSACK
1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING
OR:
OR:
PERIPHERAL
BREAKPOINT OPERATION FLOW
MOTOROLA
5-33