MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 338

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SPACE[1:0] — Address Space Select
IPL[2:0] — Interrupt Priority Level
D-20
MOTOROLA
Use this option field to select an address space for the chip-select logic. The CPU32
normally operates in supervisor or user space, but interrupt acknowledge cycles must
take place in CPU space. Table D-17 shows address space bit encodings.
When SPACE[1:0] is set for CPU space (%00), chip-select logic can be used for inter-
rupt acknowledge. During an interrupt acknowledge cycle, the priority level on address
lines ADDR[3:1] is compared to the value in IPL[2:0]. If the values are the same, a
chip-select can be asserted, provided other option register conditions are met. Table
D-18 shows IPL[2:0] field encoding.
DSACK[3:0]
Table D-18 Interrupt Priority Level Field Encoding
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table D-17 Address Space Bit Encodings
Table D-16 DSACK Field Encoding
SPACE[1:0]
IPL[2:0]
00
01
10
11
Clock Cycles Required
000
001
010
011
100
101
110
111
REGISTER SUMMARY
Per Access
Interrupt Priority Level
10
11
12
13
14
15
16
—
3
4
5
6
7
8
9
2
Supervisor/User Space
Any Level
Supervisor Space
Address Space
CPU Space
User Space
1
2
3
4
5
6
7
Wait States Inserted
Fast Termination
External DSACK
Per Access
10
11
12
13
0
1
2
3
4
5
6
7
8
9
USER’S MANUAL
MC68336/376