MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 272

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13.5.6 Overload Frames
13.6 Special Operating Modes
13.6.1 Debug Mode
13-16
MOTOROLA
bit in the matching transmit message buffer is set, the TouCAN will transmit a remote
frame as a response.
A received remote frame is not stored in a receive message buffer. It is only used to
trigger the automatic transmission of a frame in response. The mask registers are not
used in remote frame ID matching. All ID bits (except RTR) of the incoming received
frame must match for the remote frame to trigger a response transmission.
Overload frame transmissions are not initiated by the TouCAN unless certain condi-
tions are detected on the CAN bus. These conditions include:
The TouCAN module has three special operating modes:
Debug mode is entered by setting the HALT bit in the CANMCR, or by assertion of the
IMB FREEZE line. In both cases, the FRZ1 bit in CANMCR must also be set to allow
HALT or FREEZE to place the TouCAN in debug mode.
Once entry into debug mode is requested, the TouCAN waits until an intermission or
idle condition exists on the CAN bus, or until the TouCAN enters the error passive or
bus off state. Once one of these conditions exists, the TouCAN waits for the comple-
tion of all internal activity. When this happens, the following events occur:
After engaging one of the mechanisms to place the TouCAN in debug mode, the user
must wait for the FRZACK bit to be set before accessing any other registers in the
TouCAN, otherwise unpredictable operation may occur.
To exit debug mode, the IMB FREEZE line must be negated or the HALT bit in
CANMCR must be cleared.
• Detection of a dominant bit in the first or second bit of intermission.
• Detection of a dominant bit in the seventh (last) bit of the end-of-frame (EOF) field
• Detection of a dominant bit in the eighth (last) bit of the error frame delimiter or
• Debug mode
• Low-power stop mode
• Auto power save mode
• The TouCAN stops transmitting/receiving frames.
• The prescaler is disabled, thus halting all CAN bus communication.
• The TouCAN ignores its RX pins and drives its TX pins as recessive.
• The TouCAN loses synchronization with the CAN bus and the NOTRDY and
• The CPU32 is allowed to read and write the error counter registers.
in receive frames.
overload frame delimiter.
FRZACK bits in CANMCR are set.
CAN 2.0B CONTROLLER MODULE (TouCAN)
USER’S MANUAL
MC68336/376