MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 254

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

12.4 TPURAM Privilege Level
12.5 Normal Operation
12.6 Standby Operation
12-2
MOTOROLA
TRAMBAR can be written only once after a reset. This prevents runaway software
from accidentally re-mapping the array. Because the locking mechanism is activated
by the first write after a reset, the base address field should be written in a single word
operation. Writing only one-half of the register prevents the other half from being
written.
The RASP field in TRAMMCR specifies whether access to the TPURAM can be made
from supervisor mode only, or from either user or supervisor mode. If supervisor-only
access is specified, an access from user mode is ignored by the TPURAM control logic
and can be decoded externally. Refer to 4.7 Privilege Levels and 5.5.1.7 Function
Codes for more information concerning privilege levels.
During normal operation, the TPURAM control registers and array can be accessed
by the CPU32, by byte, word, or long word. A byte or aligned word access takes one
bus cycle (two system clock cycles). A long word access requires two bus cycles.
Misaligned accesses are not permitted by the CPU32 and will result in an address
error exception. Refer to 5.6 Bus Operation for more information concerning access
times. The TPU cannot access the array and has no effect on the operation of the
TPURAM during normal operation.
Standby mode maintains the RAM array when the MCU main power supply is turned
off.
Relative voltage levels of the V
in standby mode. TPURAM circuitry switches to the standby power source when spec-
ified limits are exceeded. The TPURAM is essentially powered by the power supply
pin with the greatest voltage (for example, V
voltage levels are maintained during the transition, there is no loss of memory when
switching occurs. The RAM array cannot be accessed while the TPURAM is powered
from V
I
the time V
standby operation. This occurs within the voltage range V
V. Typically, I
sition period.
Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for standby switching and
power consumption specifications.
SB
(SRAM standby current) may exceed specified maximum standby current during
STBY
DD
. If standby operation is not desired, connect the V
makes the transition from normal operating level to the level specified for
SB
peaks when V
STANDBY RAM WITH TPU EMULATION
DD
DD
and V
V
SB
STBY
– 1.5 V, and averages 1.0 mA over the tran-
DD
pins determine whether the TPURAM is
or V
STBY
). If specified standby supply
SB –
STBY
0.5 V V
pin to the V
USER’S MANUAL
DD
MC68336/376
V
SS
SS
pin.
0.5