MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 343

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

BOOT— Boot ROM Control
LOCK — Lock Registers
EMUL — Emulation Mode Control
ASPC[1:0] — ROM Array Space
WAIT[1:0] — Wait States
MC68336/376
USER’S MANUAL
Reset state of BOOT is specified at mask time. Bootstrap operation is overridden if
STOP = 1 at reset. This is a read-only bit.
The reset state of LOCK is specified at mask time. If the reset state of the LOCK is
zero, it can be set once after reset to allow protection of the registers after initialization.
Once the LOCK bit is set, it cannot be cleared again until after a reset. LOCK protects
the ASPC and WAIT fields, as well as the ROMBAL and ROMBAH registers. ASPC,
ROMBAL and ROMBAH are also protected by the STOP bit.
The MC68376 does not support emulation mode, therefore, this bit reads zero. Writes
have no effect.
ASPC can be written only if LOCK = 0 and STOP = 1. ASPC1 places the ROM array
in either supervisor or unrestricted space. ASPC0 determines if the array resides in
program space only or with program and data space. The reset state of ASPC[1:0] is
specified at mask time. Table D-22 shows ASPC[1:0] encoding.
WAIT[1:0] specifies the number of wait states inserted by the MRM during ROM array
accesses. The reset state of WAIT[1:0] is specified at mask time. WAIT[1:0] can be
written only if LOCK = 0 and STOP = 1. Table D-23 shows WAIT[1:0] encoding.
0 = ROM responds to bootstrap word locations during reset vector fetch.
1 = ROM does not respond to bootstrap word locations during reset vector fetch.
0 = Write lock disabled. Protected registers and fields can be written.
1 = Write lock enabled. Protected registers and fields cannot be written.
0 = Normal ROM operation
Table D-22 ROM Array Space Field
ASPC[1:0]
WAIT[1:0]
Table D-23 Wait States Field
00
01
10
11
00
01
10
11
REGISTER SUMMARY
Unrestricted program and data
Supervisor program and data
Cycles per Transfer
Unrestricted program
Supervisor program
State Specified
3
4
5
2
MOTOROLA
D-25