MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 17

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MC68376BGMAB20

Manufacturer Part Number
MC68376BGMAB20
Description
IC MCU 32BIT 8K ROM 160-QFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Datasheets

Specifications of MC68376BGMAB20

Core Processor
CPU32
Core Size
32-Bit
Speed
20MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
18
Program Memory Type
ROMless
Ram Size
7.5K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
160-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68376BGMAB20
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Figure
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MC68336/376
USER’S MANUAL
MC68336/376 Block Diagram ........................................................................ 3-4
MC68336 Pin Assignments for 160-Pin Package .......................................... 3-5
MC68376 Pin Assignments for 160-Pin Package .......................................... 3-6
MC68336/376 Address Map ......................................................................... 3-13
Overall Memory Map .................................................................................... 3-15
Separate Supervisor and User Space Map .................................................. 3-16
Supervisor Space (Separate Program/Data Space) Map ............................ 3-17
User Space (Separate Program/Data Space) Map ...................................... 3-18
CPU32 Block Diagram ................................................................................... 4-2
User Programming Model .............................................................................. 4-3
Supervisor Programming Model Supplement ................................................. 4-4
Data Organization in Data Registers .............................................................. 4-5
Address Organization in Address Registers ................................................... 4-6
Memory Operand Addressing ........................................................................ 4-8
Loop Mode Instruction Sequence ................................................................. 4-15
Common In-Circuit Emulator Diagram ......................................................... 4-19
Bus State Analyzer Configuration ................................................................ 4-19
Debug Serial I/O Block Diagram .................................................................. 4-24
BDM Serial Data Word ................................................................................. 4-25
BDM Connector Pinout ................................................................................. 4-25
System Integration Module Block Diagram .................................................... 5-2
System Clock Block Diagram ......................................................................... 5-4
System Clock Oscillator Circuit ...................................................................... 5-5
System Clock Filter Networks ........................................................................ 5-6
LPSTOP Flowchart ....................................................................................... 5-13
System Protection Block .............................................................................. 5-14
Periodic Interrupt Timer and Software Watchdog Timer .............................. 5-17
MCU Basic System ...................................................................................... 5-20
Operand Byte Order ..................................................................................... 5-25
Word Read Cycle Flowchart ......................................................................... 5-28
Write Cycle Flowchart .................................................................................. 5-29
CPU Space Address Encoding .................................................................... 5-31
Breakpoint Operation Flowchart ................................................................... 5-33
LPSTOP Interrupt Mask Level ...................................................................... 5-34
Bus Arbitration Flowchart for Single Request ............................................... 5-39
Preferred Circuit for Data Bus Mode Select Conditioning ............................ 5-43
Alternate Circuit for Data Bus Mode Select Conditioning ............................. 5-44
Power-On Reset ........................................................................................... 5-49
Basic MCU System ...................................................................................... 5-55
Chip-Select Circuit Block Diagram ............................................................... 5-56
CPU Space Encoding for Interrupt Acknowledge ......................................... 5-61
LIST OF ILLUSTRATIONS
Title
MOTOROLA
Page
xvii

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