MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 255

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

12.7 Low-Power Stop Operation
12.8 Reset
12.9 TPU Microcode Emulation
MC68336/376
USER’S MANUAL
Setting the STOP bit in TRAMMCR places the TPURAM in low-power stop mode. In
low-power stop mode, the array retains its contents, but cannot be read or written by
the CPU32. STOP can be written only when the processor is operating in supervisor
mode. STOP is set during resets. Low-power stop mode is exited by clearing STOP.
The TPURAM module will switch to standby mode while it is in low-power mode, pro-
vided the operating constraints discussed above are met.
Reset places the TPURAM in low-power stop mode, enables supervisor mode access
only, clears the base address register, and disables the array. These actions make it
possible to write a new base address into the base address register.
When a synchronous reset occurs while a byte or word TPURAM access is in
progress, the access is completed. If reset occurs during the first word access of a
long-word operation, only the first word access is completed. If reset occurs during the
second word access of a long-word operation, the entire access is completed. Data
being read from or written to the TPURAM may be corrupted by asynchronous reset.
Refer to 5.7 Reset for more information concerning resets.
The TPURAM array can emulate the microcode ROM in the TPU module. This pro-
vides a means for developing custom TPU code. The TPU selects TPU emulation
mode.
The TPU is connected to the TPURAM via a dedicated bus. While the TPURAM array
is in TPU emulation mode, the access timing of the TPURAM module matches the tim-
ing of the TPU microcode ROM to ensure accurate emulation. Normal accesses
through the IMB are inhibited and the control registers have no effect, allowing external
RAM to emulate the TPURAM at the same addresses. Refer to SECTION 11 TIME
PROCESSOR UNIT and to the TPU Reference Manual (TPURM/AD) for more infor-
mation.
STANDBY RAM WITH TPU EMULATION
MOTOROLA
12-3