MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 411

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

RXGMSKHI — Receive Global Mask Register High
RXGMSKLO — Receive Global Mask Register Low
D.10.9 Receive Global Mask Registers
D.10.10 Receive Buffer 14 Mask Registers
RX14MSKHI — Receive Buffer 14 Mask Register High
RX14MSKLO — Receive Buffer 14 Mask Register Low
D.10.11 Receive Buffer 15 Mask Registers
RX15MSKHI — Receive Buffer 15 Mask Register High
RX15MSKLO — Receive Buffer 15 Mask Register Low
MC68336/376
USER’S MANUAL
MID28
MID14
31
15
1
1
RESET:
RESET:
The receive global mask registers use four bytes. The mask bits are applied to all
receive-identifiers, excluding receive-buffers 14-15, which have their own specific
mask registers.
Base ID mask bits MID[28:18] are used to mask standard or extended format frames.
Extended ID bits MID[17:0] are used to mask only extended format frames.
The RTR/SRR bit of a received frame is never compared to the corresponding bit in
the message buffer ID field. However, remote request frames (RTR = 1) once
received, are never stored into the message buffers. RTR mask bit locations in the
mask registers (bits 20 and 0) are always zero, regardless of any write to these bits.
The IDE bit of a received frame is always compared to determine if the message
contains a standard or extended identifier. Its location in the mask registers (bit 19) is
always one, regardless of any write to this bit.
The receive buffer 14 mask registers have the same structure as the receive global
mask registers and are used to mask buffer 14.
The receive buffer 15 mask registers have the same structure as the receive global
mask registers and are used to mask buffer 15.
MID27
MID13
30
14
1
1
MID26
MID12
29
13
1
1
MID25
MID11
28
12
1
1
MID24
MID10
27
11
1
1
MID23
MID9
26
10
1
1
MID22
MID8
REGISTER SUMMARY
25
1
9
1
MID21
MID7
24
1
8
1
MID20
MID6
23
1
7
1
MID19
MID5
22
1
6
1
MID18
MID4
21
1
5
1
MID3
20
0
0
4
1
MID2
19
1
1
3
1
MID17
MID1
18
1
2
1
$YFF090
$YFF092
$YFF09A
MOTOROLA
$YFF094
$YFF096
$YFF098
MID16
MID0
17
1
1
1
MID15
D-93
16
1
0
0
0