MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 414

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

IMASK — Interrupt Mask Register
IFLAG — Interrupt Flag Register
ERRINT — Error Interrupt
WAKEINT — Wake Interrupt
D.10.13 Interrupt Mask Register
D.10.14 Interrupt Flag Register
D-96
MOTOROLA
15
15
0
0
RESET:
RESET:
The ERRINT bit is used to request an interrupt when the TouCAN detects a transmit
or receive error.
To clear this bit, first read it as a one, then write as a zero. Writing a one has no effect.
The WAKEINT bit indicates that bus activity has been detected while the TouCAN
module is in low-power stop mode.
IMASK contains two 8-bit fields, IMASKH and IMASKL. IMASK can be accessed with
a 16-bit read or write, and IMASKH and IMASKL can be accessed with byte reads or
writes.
IMASK contains one interrupt mask bit per buffer. It allows the CPU32 to designate
which buffers will generate interrupts after successful transmission/reception. Setting
a bit in IMASK enables interrupt requests for the corresponding message buffer.
IFLAG contains two 8-bit fields, IFLAGH and IFLAGL. IFLAG can be accessed with a
16-bit read or write, and IFLAGH and IFLAGL can be accessed with byte reads or
writes.
IFLAG contains one interrupt flag bit per buffer. Each successful transmission/recep-
tion sets the corresponding IFLAG bit and, if the corresponding IMASK bit is set, an
interrupt request will be generated.
0 = No error interrupt request.
1 = If an event which causes one of the error bits in the error and status register to
0 = No wake interrupt requested.
1 = When the TouCAN is in low-power stop mode and a recessive to dominant tran-
14
14
0
0
be set occurs, the error interrupt bit is set. If the ERRMSK bit in CANCTRL0 is
set, an interrupt request is generated.
sition is detected on the CAN bus, this bit is set. If the WAKEMSK bit is set in
CANMCR, an interrupt request is generated.
13
13
0
0
12
12
0
0
IMASKH
IFLAGH
11
11
0
0
10
10
0
0
REGISTER SUMMARY
9
0
9
0
8
0
8
0
7
0
7
0
6
0
6
0
5
0
5
0
4
0
4
0
IMASKL
IFLAGL
3
0
3
0
USER’S MANUAL
2
0
2
0
MC68336/376
$YFF0A2
$YFF0A4
1
0
1
0
0
0
0
0