MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 72

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4.10.4.1 External BKPT Signal
4.10.4.2 BGND Instruction
4.10.4.3 Double Bus Fault
4.10.4.4 Peripheral Breakpoints
4.10.5 Entering BDM
4-20
MOTOROLA
Table 4-4 summarizes the processing of each source for both enabled and disabled
cases. As shown in Table 4-4, the BKPT instruction never causes a transition into
BDM.
Once enabled, BDM is initiated whenever assertion of BKPT is acknowledged. If BDM
is disabled, a breakpoint exception (vector $0C) is acknowledged. The BKPT input has
the same timing relationship to the data strobe trailing edge as does read cycle data.
There is no breakpoint acknowledge bus cycle when BDM is entered.
An illegal instruction, $4AFA, is reserved for use by development tools. The CPU32
defines $4AFA (BGND) to be a BDM entry point when BDM is enabled. If BDM is
disabled, an illegal instruction trap is acknowledged.
The CPU32 normally treats a double bus fault, or two bus faults in succession, as a
catastrophic system error, and halts. When this condition occurs during initial system
debug (a fault in the reset logic), further debugging is impossible until the problem is
corrected. In BDM, the fault can be temporarily bypassed, so that the origin of the fault
can be isolated and eliminated.
CPU32 peripheral breakpoints are implemented in the same way as external break-
points — peripherals request breakpoints by asserting the BKPT signal. Consult the
appropriate peripheral user’s manual for additional details on the generation of
peripheral breakpoints.
When the processor detects a breakpoint or a double bus fault, or decodes a BGND
instruction, it suspends instruction execution and asserts the FREEZE output. This is
the first indication that the processor has entered BDM. Once FREEZE has been as-
serted, the CPU enables the serial communication hardware and awaits a command.
The CPU writes a unique value indicating the source of BDM transition into temporary
register A (ATEMP) as part of the process of entering BDM. A user can poll ATEMP
and determine the source (refer to Table 4-5) by issuing a read system register com-
mand (RSREG). ATEMP is used in most debugger commands for temporary storage
Double Bus Fault
BGND Instruction
BKPT Instruction
Source
BKPT
Table 4-4 BDM Source Summary
CENTRAL PROCESSOR UNIT
Opcode Substitution/
Illegal Instruction
BDM Enabled
Background
Background
Background
Breakpoint Exception
Opcode Substitution/
Illegal Instruction
Illegal Instruction
BDM Disabled
Halted
USER’S MANUAL
MC68336/376