MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 239

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.3.6 Emulation Support
11.3.7 TPU Interrupts
MC68336/376
USER’S MANUAL
effect at the same time. Parameter RAM hardware supports coherent access of two
adjacent 16-bit parameters. The host CPU must use a long-word operation to guaran-
tee coherency.
Although factory-programmed time functions can perform a wide variety of control
tasks, they may not be ideal for all applications. The TPU provides emulation capability
that allows the user to develop new time functions. Emulation mode is entered by set-
ting the EMU bit in TPUMCR. In emulation mode, an auxiliary bus connection is made
between TPURAM and the TPU, and access to TPURAM via the intermodule bus is
disabled. A 9-bit address bus, a 32-bit data bus, and control lines transfer information
between the modules. To ensure exact emulation, RAM module access timing re-
mains consistent with access timing of the TPU microcode ROM control store.
To support changing TPU application requirements, Motorola has established a TPU
function library. The function library is a collection of TPU functions written for easy
assembly in combination with each other or with custom functions. Refer to Motorola
Programming Note TPUPN00/D, Using the TPU Function Library and TPU Emulation
Mode for information about developing custom functions and accessing the TPU func-
tion library. Refer to the TPU Reference Manual (TPURM/AD) and the Motorola TPU
Literature Package (TPULITPAK/D) for more information about specific functions.
Each of the TPU channels can generate an interrupt service request. Interrupts for
each channel must be enabled by writing to the appropriate control bit in the channel
interrupt enable register (CIER). The channel interrupt status register (CISR) contains
one interrupt status flag per channel. Time functions set the flags. Setting a flag bit
causes the TPU to make an interrupt service request if the corresponding channel in-
terrupt enable bit is set and the interrupt request level is non-zero.
The value of the channel interrupt request level (CIRL) field in the TPU interrupt
configuration register (TICR) determines the priority of all TPU interrupt service re-
quests. CIRL values correspond to MCU interrupt request signals IRQ[7:1]. IRQ7 is
the highest-priority request signal; IRQ1 has the lowest priority. Assigning a value of
%111 to CIRL causes IRQ7 to be asserted when a TPU interrupt request is made;
lower field values cause corresponding lower-priority interrupt request signals to be
asserted. Assigning CIRL a value of %000 disables all interrupts.
The CPU32 recognizes only interrupt requests of a priority greater than the value
contained in the interrupt priority (IP) mask in the status register. When the CPU32
acknowledges an interrupt request, the priority of the acknowledged interrupt is written
to the IP mask and is driven out onto the IMB address lines.
When the IP mask value driven out on the address lines is the same as the CIRL value,
the TPU contends for arbitration priority. The IARB field in TPUMCR contains the TPU
arbitration number. Each module that can make an interrupt service request must be
assigned a unique non-zero IARB value in order to implement an arbitration scheme.
TIME PROCESSOR UNIT
MOTOROLA
11-5