MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 237

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.2.3 Scheduler
11.2.4 Microengine
11.2.5 Host Interface
11.2.6 Parameter RAM
11.3 TPU Operation
MC68336/376
USER’S MANUAL
When a service request is received, the scheduler determines which TPU channel is
serviced by the microengine. A channel can request service for one of four reasons:
for host service, for a link to another channel, for a match event, or for a capture event.
The host system assigns each active channel one of three priorities: high, middle, or
low. When multiple service requests are received simultaneously, a priority-scheduling
mechanism grants service based on channel number and assigned priority.
The microengine is composed of a control store and an execution unit. Control-store
ROM holds the microcode for each factory-masked time function. When assigned to a
channel by the scheduler, the execution unit executes microcode for a function as-
signed to that channel by the CPU32. Microcode can also be executed from the
TPURAM module instead of the control store. The TPURAM allows emulation and de-
velopment of custom TPU microcode without the generation of a microcode ROM
mask. Refer to 11.3.6 Emulation Support for more information.
The host interface registers allow communication between the CPU32 and the TPU,
both before and during execution of a time function. The registers are accessible from
the IMB through the TPU bus interface unit. Refer to 11.6 Host Interface Registers
and D.8 Time Processor Unit (TPU) for register bit/field definitions and address map-
ping.
Parameter RAM occupies 256 bytes at the top of the system address map. Channel
parameters are organized as 128 16-bit words. Although all parameter word locations
in RAM can be accessed by all channels, only 100 are normally used: channels 0 to
13 use six parameter words, while channels 14 and 15 each use eight parameter
words. The parameter RAM address map in D.8.15 TPU Parameter RAM shows how
parameter words are organized in memory.
The CPU32 specifies function parameters by writing to the appropriate RAM address.
The TPU reads the RAM to determine channel operation. The TPU can also store in-
formation to be read by the CPU32 in the parameter RAM. Detailed descriptions of the
parameters required by each time function are beyond the scope of this manual. Refer
to the TPU Reference Manual (TPURM/AD) and the Motorola TPU Literature Package
(TPULITPAK/D) for more information.
All TPU functions are related to one of the two 16-bit time bases. Functions are syn-
thesized by combining sequences of match events and capture events. Because the
primitives are implemented in hardware, the TPU can determine precisely when a
match or capture event occurs, and respond rapidly. An event register for each chan-
nel provides for simultaneity of match/capture event occurrences on all channels.
TIME PROCESSOR UNIT
MOTOROLA
11-3