MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 432

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

TPU
MOTOROLA
I-16
special operating modes 13-16
transmit process 13-12
A mask functions 11-6
address map D-73
block diagram 11-1
components 11-2
features 3-2
FREEZE flag (TPUF) D-77
function library 11-5
G mask functions 11-10
host interface 11-3
interrupts 11-5
microengine 11-3
operation 11-3
module configuration register (CANMCR) D-85
receive
RX/TX error counter registers (RXECTR/TXEC-
test configuration register (CANTCR) D-88
auto power save mode 13-18
debug mode 13-16
low-power stop mode 13-17
discrete input/output (DIO) 11-6
input capture/input transition counter (ITC) 11-6
output compare (OC) 11-7
period
position-synch pulse generator (PSP) 11-8
pulse width modulation (PWM) 11-7
quadrature decode (QDEC) 11-10
stepper motor (SM) 11-9
synch pw modulation (SPWM) 11-7
brushless motor commutation (COMM) 11-12
fast quadrature decode (FQD) 11-12
frequency measurement (FQM) 11-13
hall effect decode (HALLD) 11-13
multichannel pulse width modulation (PCPWM)
new input capture/transition counter (NITC)
programmable time accumulator (PTA) 11-11
queued output match (QOM) 11-11
table stepper motor (TSM) 11-10
universal
coherency 11-4
emulation support 11-5
event timing 11-3
interchannel communication 11-4
mask register (IMASK) D-96
buffer 14 mask registers (RX14MSKHI/LO)
buffer 15 mask registers (RX15MSKHI/LO)
global mask registers (RXGMSKLO/HI
/pw accumulator (PPWA) 11-9
measurement
TR) D-97
add transition detect (PMA) 11-8
missing transition detect (PMM) 11-8
11-11
11-11
(UART) 11-12
asynchronous
D-93
D-93
D-93
receiver/transmitter
TPU Reference Manual 11-3, 11-16, 11-17
TPUF D-77
TPUMCR 11-13, D-73
TPURAM
t
t
TR D-54
Trace
TRAMBAR 12-1, D-82
TRAMMCR 12-1, D-82
PWMAX
PWMIN
overview 11-1
parameter RAM 11-3, D-80
registers
scheduler 11-3
time
timer channels 11-2
timing (electricals) A-26
address map D-82
array
features 3-2
general 12-1
operation
privilege level 12-2
register block 12-1
registers
reset 12-3
TPU microcode emulation 12-3
enable field (T) D-3
on instruction execution 4-18
10-17
10-17
programmable channel service priority 11-4
address map D-81
channel
decoded channel number register (DCNR) D-80
development
host
link register (LR) D-80
module configuration register (TPUMCR) D-73
service grant latch register (SGLR) D-80
test configuration register (TCR) D-75
TPU interrupt configuration register (TICR) D-77
bases 11-2
address mapping 12-1
base address (ADDR) D-83
space (RASP) D-82
normal 12-2
standby 12-2
base address and status register (TRAMBAR)
module configuration register (TRAMMCR)
test register (TRAMTST) D-82
function select registers (CFSR) D-78
interrupt
priority registers (CPR) D-79
support control register (DSCR) D-75
support status register (DSSR) D-76
sequence registers (HSQR) D-78
service request registers (HSSR) D-79
enable register (CIER) 11-5, D-77
status register (CISR) 11-5, D-80
D-82
D-82
USER’S MANUAL
MC68336/376