MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 70

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4.10.1 M68000 Family Development Support
4.10.2 Background Debug Mode
4-18
MOTOROLA
All M68000 Family members include features to facilitate applications development.
These features include the following:
Trace on Instruction Execution — M68000 Family processors include an instruction-
by-instruction tracing facility as an aid to program development. The MC68020,
MC68030, MC68040, and CPU32 also allow tracing only of those instructions causing
a change in program flow. In the trace mode, a trace exception is generated after an
instruction is executed, allowing a debugger program to monitor the execution of a pro-
gram under test.
Breakpoint Instruction — An emulator may insert software breakpoints into the target
code to indicate when a breakpoint has occurred. On the MC68010, MC68020,
MC68030, and CPU32, this function is provided via illegal instructions, $4848–$484F,
to serve as breakpoint instructions.
Unimplemented Instruction Emulation — During instruction execution, when an at-
tempt is made to execute an illegal instruction, an illegal instruction exception occurs.
Unimplemented instructions (F-line, A-line, . . .) utilize separate exception vectors to
permit efficient emulation of unimplemented instructions in software.
Microcomputer systems generally provide a debugger, implemented in software, for
system analysis at the lowest level. The background debug mode (BDM) on the
CPU32 is unique in that the debugger has been implemented in CPU microcode.
BDM incorporates a full set of debugging options: registers can be viewed or altered,
memory can be read or written to, and test features can be invoked.
A resident debugger simplifies implementation of an in-circuit emulator. In a common
setup (refer to Figure 4-8), emulator hardware replaces the target system processor.
A complex, expensive pod-and-cable interface provides a communication path be-
tween the target system and the emulator.
By contrast, an integrated debugger supports use of a bus state analyzer (BSA) for
incircuit emulation. The processor remains in the target system (refer to Figure 4-9)
and the interface is simplified. The BSA monitors target processor operation and the
on-chip debugger controls the operating environment. Emulation is much “closer” to
target hardware, and many interfacing problems (for example, limitations on high-
frequency operation, AC and DC parametric mismatches, and restrictions on cable
length) are minimized.
CENTRAL PROCESSOR UNIT
USER’S MANUAL
MC68336/376