MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 225

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.7.2.2 Using the MCSM as a Free-Running Counter
10.7.3 MCSM Clock Sources
10.7.4 MCSM External Event Counting
10.7.5 MCSM Time Base Bus Driver
10.7.6 MCSM Interrupts
MC68336/376
USER’S MANUAL
Although the MCSM is a modulus counter, it can operate like a free-running counter
by loading the modulus register with $0000.
The MCSM has eight software selectable counter clock sources, including:
The clock source is selected by the CLK[2:0] bits in MCSMSIC. When the CLK[2:0]
bits are being changed, internal circuitry guarantees that spurious edges occurring on
the CTM2C pin do not affect the MCSM. The read only IN2 bit in MCSMSIC reflects
the state of CTM2C. This pin is Schmitt-triggered, and is synchronized with the system
clock. The maximum allowable frequency for a clock signal input on CTM2C is f
When an external clock source is selected, the MCSM can act as an event counter
simply by counting the number of events occurring on the CTM2C input pin. Alterna-
tively, the MCSM can be programmed to generate an interrupt when a predefined
number of events have been counted. This is done by presetting the counter with the
two’s complement value of the desired number of events.
The DRVA and DRVB bits in MCSMSIC select the time base bus to be driven. Which
of the time base buses is driven depends on where the MCSM is physically placed in
any particular CTM implementation. Refer to Figure 10-1 and Table 10-1 for more
information.
The MCSM can optionally request an interrupt when its counter overflows and the
COF bit in MCSMSIC is set. To enable interrupts, set the IL[2:0] field in the MCSMSIC
to a non-zero value. The CTM4 compares the CPU32 IP mask value to the priority of
the requested interrupt designated by IL[2:0] to determine whether it should contend
for arbitration priority. During arbitration, the BIUSM provides the arbitration value
specified by IARB[2:0] in BIUMCR and IARB3 in MCSMSIC. If the CTM4 wins arbitra-
tion, it responds with a vector number generated by concatenating VECT[7:6] in
BIUMCR and the six low-order bits specified by the number of the submodule request-
ing service. Thus, for MCSM12 in CTM4, six low-order bits would be 12 in decimal, or
%001100 in binary.
• Six CPSM prescaler outputs (PCLK[1:6])
• Rising edge on the CTM2C input
• Falling edge on the CTM2C input
Two time base buses should not be driven at the same time.
CONFIGURABLE TIMER MODULE 4
WARNING
MOTOROLA
sys
10-9
/4.