MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 389
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MC68376BGMAB20
Manufacturer Part Number
MC68376BGMAB20
Description
IC MCU 32BIT 8K ROM 160-QFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Specifications of MC68376BGMAB20
Core Processor
CPU32
Core Size
32-Bit
Speed
20MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
18
Program Memory Type
ROMless
Ram Size
7.5K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
160-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68376BGMAB20
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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D.7.15 PWM Period Register
PWM5A1 — PWM5A Period Register
PWM6A1 — PWM6A Period Register
PWM7A1 — PWM7A Period Register
PWM8A1 — PWM8A Period Register
D.7.16 PWM Pulse Width Register
PWM5B1 — PWM5 Pulse Width Register
PWM6B1 — PWM6 Pulse Width Register
PWM7B1 — PWM7 Pulse Width Register
PWM8B1 — PWM8 Pulse Width Register
MC68336/376
USER’S MANUAL
15
15
U
U
RESET:
RESET:
The PWMA1 register contains the period value for the next cycle of the PWM output
waveform. When the PWMSM is enabled, a period value written to PWMA1 is loaded
into PWMA2 at the end of the current period or when the LOAD bit in PWMSIC is writ-
ten to one. If the PWMSM is disabled, a period value written to PWMA1 is loaded into
PWMA2 on the next half cycle of the MCU system clock. PWMA2 is a temporary reg-
ister that is used to smoothly update the PWM period value; it is not user-accessible.
The PWMSM hardware does not modify the contents of PWMA1 at any time.
14
14
U
U
13
13
U
U
CLK2
0
0
0
0
1
1
1
1
12
12
U
U
Table D-50 PWMSM Divide By Options
11
11
U
U
CLK1
0
0
1
1
0
0
1
1
10
10
U
U
CLK0
REGISTER SUMMARY
U
U
9
9
0
1
0
1
0
1
0
1
U
U
8
8
(CPCR DIV23 = 0)
PCLK1 = f
f
f
f
f
f
sys
sys
f
f
f
sys
sys
sys
sys
sys
sys
U
U
7
7
128
512
sys
16
32
64
2
4
8
U
U
6
6
2
U
U
5
5
(CPCR DIV23 = 0)
PCLK1 = f
f
f
f
f
f
f
sys
sys
f
f
sys
sys
sys
sys
4
U
4
U
sys
sys
192
768
sys
12
24
48
96
3
6
U
U
3
3
2
U
U
2
2
$YFF42A
$YFF43A
$YFF42C
$YFF43C
MOTOROLA
$YFF432
$YFF442
$YFF434
$YFF444
U
U
1
1
D-71
U
U
0
0
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