MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 119

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.7.3 Reset Mode Selection
MC68336/376
USER’S MANUAL
All resets are gated by CLKOUT. Resets are classified as synchronous or asynchro-
nous. An asynchronous reset can occur on any CLKOUT edge. Reset sources that
cause an asynchronous reset usually indicate a catastrophic failure. As a result, the
reset control logic responds by asserting reset to the system immediately. (A system
reset, however, caused by the CPU32 RESET instruction, is asynchronous but does
not indicate any type of catastrophic failure).
Synchronous resets are timed to occur at the end of bus cycles. The SIM bus monitor
is automatically enabled for synchronous resets. When a bus cycle does not terminate
normally, the bus monitor terminates it.
Refer to Table 5-14 for a summary of reset sources.
Internal single byte or aligned word writes are guaranteed valid for synchronous
resets. External writes are also guaranteed to complete, provided the external config-
uration logic on the data bus is conditioned as shown in Figure 5-16.
The logic states of certain data bus pins during reset determine SIM operating config-
uration. In addition, the state of the MODCLK pin determines system clock source and
the state of the BKPT pin determines what happens during subsequent breakpoint as-
sertions. Table 5-15 is a summary of reset mode selection options.
Software watchdog
1. XTRST (external reset) drives the external reset pin.
2. CLKRST (clock reset) resets the clock module.
3. MSTRST (master reset) goes to all other internal circuits.
4. SYSRST (system reset) indicates to internal circuits that the CPU32 has
Loss of clock
Power up
External
System
HALT
Type
executed a RESET instruction.
Test
External
Source
Monitor
Monitor
CPU32
Clock
Test
EBI
Table 5-14 Reset Source Summary
SYSTEM INTEGRATION MODULE
Timing
Asynch
Asynch
Asynch
Asynch
Synch
Synch
Synch
Internal HALT assertion
(e.g. double bus fault)
RESET instruction
Loss of reference
RESET pin
Test mode
Time out
Cause
V
DD
MSTRST
MSTRST
MSTRST
MSTRST
MSTRST
MSTRST
—
Reset Lines Asserted by
Controller
CLKRST
CLKRST
CLKRST
CLKRST
CLKRST
—
—
EXTRST
EXTRST
EXTRST
EXTRST
EXTRST
EXTRST
EXTRST
MOTOROLA
5-41