MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 230

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.9.3 PWMSM Counter
10.9.4 PWMSM Period Registers and Comparator
10-14
MOTOROLA
The 16-bit up counter in the PWMSM provides the time base for the PWM output sig-
nal. The counter is held in the $0001 state after reset or when the PWMSM is disabled.
When the PWMSM is enabled, the counter begins counting at the rate selected by
CLK[2:0] in PWMSIC. Each time the counter matches the contents of the period reg-
ister, the counter is preset to $0001 and starts to count from that value. The counter
can be read at any time from the PWMC register without affecting its value. Writing to
the counter has no effect.
The period section of the PWMSM consists of two 16-bit period registers (PWMA1 and
PWMA2) and one 16-bit comparator. PWMA2 holds the current PWM period value,
and PWMA1 holds the next PWM period value. The next period of the output PWM
signal is established by writing a value into PWMA1. PWMA2 acts as a double buffer
for PWMA1, allowing the contents of PWMA1 to be changed at any time without af-
fecting the period of the current output signal. PWMA2 is not user accessible. PWMA1
can be read or written at any time. The new value in PWMA1 is transferred to PWMA2
on the next full cycle of the PWM output or when a one is written to the LOAD bit in
PWMSIC.
The comparator continuously compares the contents of PWMA2 with the value in the
PWMSM counter. When a match occurs, the state sequencer sets the output flip-flop
and resets the counter to $0001.
Period values $0000 and $0001 are special cases. When PWMA2 contains $0000, an
output period of 65536 PWM clock periods is generated.
When PWMA2 contains $0001, a period match occurs on every PWM clock period.
The counter never increments beyond $0001, and the output level never changes.
Values of $0002 in the period register (PWMA2) and $0001 in the
pulse width register (PWMB2) result in the maximum possible output
frequency for a given PWM counter clock frequency.
CLK2
0
0
0
0
1
1
1
1
Table 10-4 PWMSM Divide By Options
CLK1
0
0
1
1
0
0
1
1
CONFIGURABLE TIMER MODULE 4
CLK0
0
1
0
1
0
1
0
1
(CPCR DIV23 = 0)
PCLK1 = f
NOTE
f
f
f
f
f
sys
sys
f
f
sys
sys
sys
f
sys
sys
sys
128
512
sys
16
32
64
2
4
8
2
(CPCR DIV23 = 0)
PCLK1 = f
f
f
f
f
f
f
sys
sys
f
f
sys
sys
sys
sys
sys
sys
192
768
sys
12
24
48
96
3
6
3
USER’S MANUAL
MC68336/376