HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 983

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

TIOR1—Timer I/O Control Register 1
Bit
Initial value
Read/Write
:
:
:
TGR1B I/O control
0 0
1
IOB3
R/W
7
0
1 0 0
0
1
0 0
1 0
1 0
0 0 TGR1B
1 *
*
1
1
1
1
1
*
IOB2
R/W
TGR1B
is output
compare
register
is input
capture
register
6
0
TGR1A I/O control
0 0
1
1 0 0
0
1
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCB1 pin
Capture input
source is TGR0C
compare match/
input capture
IOB1
R/W
0 0
1 0
1 0
0 0 TGR1A
1 *
*
5
0
1
1
1
1
1
*
TGR1A
is output
compare
register
is input
capture
register
IOB0
R/W
4
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
TGR0C compare match/input
capture
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCA1 pin
Capture input
source is TGR0A
compare match/
input capture
H'FF22
Rev. 5.00 Jan 10, 2006 page 957 of 1042
IOA3
R/W
3
0
Appendix B Internal I/O Register
IOA2
R/W
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
channel 0/TGR0A compare match/
input capture
2
0
*: Don’t care
IOA1
R/W
REJ09B0275-0500
1
0
*: Don’t care
IOA0
R/W
0
0
TPU1