HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 201

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

(2) Write after Read
If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the write cycle.
Figure 7.16 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
CS * (area A)
CS * (area B)
Note: * The CS signals are generated off-chip.
Address bus
RD
Possibility of overlap between
CS (area B) and RD
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS1 = 0)
Figure 7.16 Example of Idle Cycle Operation (2)
T
2
T
3
Bus cycle B
T
1
T
2
CS * (area A)
CS * (area B)
Address bus
Rev. 5.00 Jan 10, 2006 page 175 of 1042
RD
T
(b) Idle cycle inserted
1
Bus cycle A
(Initial value ICIS1 = 1)
T
2
Section 7 Bus Controller
T
3
REJ09B0275-0500
T
I
Bus cycle B
T
1
T
2