HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 411

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse
output group 1 (pins PO7 to PO4). However, the H8S/2626 Group and H8S/2623 Group have no
pins corresponding to pulse output group 1.
Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping operation for pulse
output group 0 (pins PO3 to PO0). However, the H8S/2626 Group and H8S/2623 Group have no
pins corresponding to pulse output group 0.
11.2.7
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1.
Port 1 is multiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG output must
be set to 1. For further information about P1DDR, see section 9.2, Port 1.
Bit 1
G1NOV
0
1
Bit 0
G0NOV
0
1
Bit
Initial value :
R/W
Port 1 Data Direction Register (P1DDR)
Description
Normal operation in pulse output group 1 (output values updated at compare match A
in the selected TPU channel)
Non-overlapping operation in pulse output group 1 (independent 1 and 0 output at
compare match A or B in the selected TPU channel)
Description
Normal operation in pulse output group 0 (output values updated at compare match A
in the selected TPU channel)
Non-overlapping operation in pulse output group 0 (independent 1 and 0 output at
compare match A or B in the selected TPU channel)
:
:
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
W
7
0
W
6
0
W
5
0
Section 11 Programmable Pulse Generator (PPG)
W
4
0
Rev. 5.00 Jan 10, 2006 page 385 of 1042
W
3
0
W
2
0
REJ09B0275-0500
W
1
0
(Initial value)
(Initial value)
W
0
0