HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 156

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 PC Break Controller (PBC)
6.2.2
BARB is the channel B break address register. The bit configuration is the same as for BARA.
6.2.3
BCRA is an 8-bit readable/writable register that controls channel A PC breaks. BCRA (1) selects
the break condition bus master, (2) specifies bits subject to address comparison masking, and (3)
specifies whether the break condition is applied to an instruction fetch or a data access. It also
contains a condition match flag.
BCRA is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is
satisfied. This flag is not cleared to 0.
Bit 7
CMFA
0
1
Bit 6—CPU Cycle/DTC Cycle Select A (CDA): Selects the channel A break condition bus
master.
Bit 6
CDA
0
1
Rev. 5.00 Jan 10, 2006 page 130 of 1042
REJ09B0275-0500
Bit
Initial value
R/W
Note: * Only 0 can be written, for flag clearing.
Break Address Register B (BARB)
Break Control Register A (BCRA)
Description
[Clearing condition]
When 0 is written to CMFA after reading CMFA = 1
[Setting condition]
When a condition set for channel A is satisfied
Description
PC break is performed when CPU is bus master
PC break is performed when CPU or DTC is bus master
R/(W) *
CMFA
0
7
CDA
R/W
6
0
BAMRA2
R/W
0
5
BAMRA1
R/W
4
0
BAMRA0
R/W
3
0
CSELA1
R/W
2
0
CSELA0
R/W
1
0
(Initial value)
(Initial value)
BIEA
R/W
0
0