HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 950

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Appendix B Internal I/O Register
TSR3—Timer Status Register 3
Rev. 5.00 Jan 10, 2006 page 924 of 1042
REJ09B0275-0500
Note: * Can only be written with 0 for flag clearing.
Bit
Initial value
Read/Write
:
:
:
—
—
7
1
Overflow flag
0 [Clearing condition]
1
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000)
TGR input capture/output compare flag D
0 [Clearing conditions]
1
—
—
6
1
• When DTC is activated by TGID interrupt, and DISEL bit in DTC’s MRB is 0
• When 0 is written to TGFD after reading TGFD = 1
[Setting conditions]
• When TCNT = TGRD while TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal while
TGRD is functioning as input capture register
TGR input capture/output compare flag C
0 [Clearing conditions]
1
• When DTC is activated by TGIC interrupt, and DISEL bit in DTC’s MRB is 0
• When 0 is written to TGFC after reading TGFC = 1
[Setting conditions]
• When TCNT = TGRC while TGRC is functioning as output compare register
• When TCNT value is transferred to TGRC by input capture signal while
TGRC is functioning as input capture register
—
—
5
0
TGR input capture/output compare flag B
0 [Clearing conditions]
1
• When DTC is activated by TGIB interrupt, and DISEL
• When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is functioning as
• When TCNT value is transferred to TGRB by input
R/(W)*
TCFV
bit in DTC’s MRB is 0
output compare register
capture signal while TGRB is functioning as input
capture register
4
0
TGR input capture/output compare flag A
0
1
H'FE85
[Clearing conditions]
• When DTC is activated by TGIA interrupt, and DISEL
• When 0 is written to TGFA after reading TGFA = 1
[Setting conditions]
• When TCNT = TGRA while TGRA is functioning as
• When TCNT value is transferred to TGRA by input
bit in DTC’s MRB is 0
output compare register
capture signal while TGRA is functioning as input
capture register
R/(W)*
TGFD
3
0
R/(W)*
TGFC
2
0
R/(W)*
TGFB
1
0
R/(W)*
TGFA
0
0
TPU3