HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 425

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.1
A single on-chip watchdog timer channel (WDT0) is provided in the H8S/2623 Group, and two
watchdog timer channels (WDT0 and WDT1) in the H8S/2626 Group. The WDT outputs an
overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter,
allowing it to overflow. At the same time, the WDT can also generate an internal reset signal for
the H8S/2626 Group or H8S/2623 Group.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
12.1.1
WDT features are listed below.
Switchable between watchdog timer mode and interval timer mode
WDTOVF output when in watchdog timer mode
If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether the LSI
is internally reset or an NMI interrupt is generated at the same time.
Interrupt generation when in interval timer mode
If the counter overflows, the WDT generates an interval timer interrupt.
WDT0 and WDT1 respectively allow eight and sixteen types of counter input clock to be
selected
The maximum interval of the WDT is given as a system clock cycle
A subclock may be selected for the input counter of WDT1.
Where a subclock is selected, the maximum interval is given as a subclock cycle
Selected clock can be output from the BUZZ output pin (WDT1)
Overview
Features
Section 12 Watchdog Timer
Rev. 5.00 Jan 10, 2006 page 399 of 1042
Section 12 Watchdog Timer
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