HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 764
HD64F2623FA20J
Manufacturer Part Number
HD64F2623FA20J
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2623FA20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 21B Power-Down Modes [H8S/2626 Group]
21B.11 Direct Transitions
21B.11.1 Overview of Direct Transitions
There are three modes, high-speed, medium-speed, and sub-active, in which the CPU executes
programs. When a direct transition is made, there is no interruption of program execution when
shifting between high-speed and sub-active modes. Direct transitions are enabled by setting the
LPWRCR DTON bit to 1, then executing the SLEEP instruction. After a transition, direct
transition interrupt exception processing starts.
(1) Direct Transitions from High-Speed Mode to Sub-Active Mode
Execute the SLEEP instruction in high-speed mode when the SBYCR SSBY bit = 1, LPWRCR
LSON bit = 1, and DTON bit = 1, and TSCR (WDT1) PSS bit = 1 to make a transition to sub-
active mode.
(2) Direct Transitions from Sub-Active Mode to High-Speed Mode
Execute the SLEEP instruction in sub-active mode when the SBYCR SSBY bit = 1, LPWRCR
LSON bit = 0, and DTON bit = 1, and TSCR (WDT1) PSS bit = 1 to make a direct transition to
high-speed mode after the time set in SBYCR STS2 to STS0 has elapsed.
21B.12
Output of the clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the clock stops at the end of the bus cycle,
and output goes high. clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, clock output is disabled and input port mode is set.
Table 21B.6 shows the state of the pin in each processing state.
Table 21B.6
DDR
PSTOP
Hardware standby mode
Software standby mode, watch
mode, and direct transition
Sleep mode and subsleep mode
High-speed mode, medium-speed
mode, and subactive mode
Rev. 5.00 Jan 10, 2006 page 738 of 1042
REJ09B0275-0500
Clock Output Disabling Function
Pin State in Each Processing State
0
—
High impedance
High impedance
High impedance
High impedance
1
0
High impedance
Fixed high
output
output
1
1
High impedance
Fixed high
Fixed high
Fixed high
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