HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 531

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.3.4
Table 14.3 shows a bit map of the registers used by the smart card interface.
Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described
below.
Table 14.3 Smart Card Interface Register Settings
Notes: — : Unused bit.
SMR Setting: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in
GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1
if of the inverse convention type.
Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. Bits BCP1 and
BCP0 select the number of basic clock periods in a 1-bit transfer interval. For details, see section
14.3.5, Clock.
The BLK bit is cleared to 0 in normal smart card interface mode, and set to 1 in block transfer
mode.
BRR Setting: BRR is used to set the bit rate. See section 14.3.5, Clock, for the method of
calculating the value to be set.
SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI.
For details, see section 13, Serial Communication Interface (SCI).
Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these
bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in
SMR is set to 1, clock output is performed. The clock output can also be fixed high or low.
Register
SMR
BRR
SCR
TDR
SSR
RDR
SCMR
*:
Register Settings
Bit 7
GM
BRR7
TIE
TDR7
TDRE
RDR7
—
The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0.
Bit 6
BLK
BRR6
RIE
TDR6
RDRF
RDR6
—
Bit 5
1
BRR5
TE
TDR5
ORER
RDR5
—
Bit 4
O/E
BRR4
RE
TDR4
ERS
RDR4
—
Bit
TDR3
Bit 3
BCP1
BRR3
0
PER
RDR3
SDIR
Rev. 5.00 Jan 10, 2006 page 505 of 1042
Section 14 Smart Card Interface
Bit 2
BCP0
BRR2
0
TDR2
TEND
RDR2
SINV
Bit 1
CKS1
BRR1
CKE1 *
TDR1
0
RDR1
—
REJ09B0275-0500
Bit 0
CKS0
BRR0
CKE0
TDR0
0
RDR0
SMIF