HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 164
HD64F2623FA20J
Manufacturer Part Number
HD64F2623FA20J
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2623FA20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
HD64F2623FA20J
Manufacturer:
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Quantity:
10 000
Part Number:
HD64F2623FA20J
Manufacturer:
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Quantity:
20 000
Part Number:
HD64F2623FA20JV
Manufacturer:
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Quantity:
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Section 6 PC Break Controller (PBC)
6.3.7
(1) When a PC break is set for an instruction fetch at the address following a BSR, JSR, JMP,
(2) When the I bit is set by an LDC, ANDC, ORC, or XORC instruction, a PC break interrupt
(3) When a PC break is set for an instruction fetch at the address following a Bcc instruction:
(4) When a PC break is set for an instruction fetch at the branch destination address of a Bcc
Rev. 5.00 Jan 10, 2006 page 138 of 1042
REJ09B0275-0500
TRAPA, RTE, or RTS instruction:
Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS
instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the
instruction fetch at the next address.
becomes valid two states after the end of the executing instruction. If a PC break interrupt is
set for the instruction following one of these instructions, since interrupts, including NMI, are
disabled for a 3-state period in the case of LDC, ANDC, ORC, and XORC, the next instruction
is always executed. For details, see section 5, Interrupt Controller.
A PC break interrupt is generated if the instruction at the next address is executed in
accordance with the branch condition, but is not generated if the instruction at the next address
is not executed.
instruction:
A PC break interrupt is generated if the instruction at the branch destination is executed in
accordance with the branch condition, but is not generated if the instruction at the branch
destination is not executed.
Additional Notes
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