HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 682

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 19 ROM (Preliminary)
19.7.3
When erasing flash memory, the single-block erase/erase-verify flowchart shown in figure 19.12
should be followed.
To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in
erase block register 1 and 2 (EBR1, EBR2) at least (x) µs after setting the SWE1 bit to 1 in
FLMCR1. Next, the watchdog timer (WDT) is set to prevent overerasing due to program
runaway, etc. Set 6.6 ms as the WDT overflow period. Preparation for entering erase mode (erase
setup) is performed next by setting the ESU1 bit in FLMCR1. The operating mode is then
switched to erase mode by setting the E1 bit in FLMCR1 after the elapse of at least (y) µs. The
time during which the E1 bit is set is the flash memory erase time. Ensure that the erase time does
not exceed (z) ms.
Note: With flash memory erasing, preprogramming (setting all memory data in the memory to
19.7.4
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the fixed erase time, clear the E1 bit in FLMCR1, then wait for at least ( ) µs
before clearing the ESU1 bit to exit erase mode. After exiting erase mode, the watchdog timer is
cleared after the elapse of ( ) µs or more. The operating mode is then switched to erase-verify
mode by setting the EV1 bit in FLMCR1. Before reading in erase-verify mode, a dummy write of
H'FF data should be made to the addresses to be read. The dummy write should be executed after
the elapse of ( ) µs or more. When the flash memory is read in this state (verify data is read in 16-
bit units), the data at the latched address is read. Wait at least ( ) µs after the dummy write before
performing this read operation. If the read data has been erased (all 1), a dummy write is
performed to the next address, and erase-verify is performed. If the read data is unerased, set erase
mode again and repeat the erase/erase-verify sequence in the same way. The maximum number of
reoperations of the erase/erase-verify sequence is indicated by the maximum erase count (N).
However, ensure that the erase/erase-verify sequence is not repeated more than (N) times. When
verification is completed, exit erase-verify mode, and wait for at least ( ) µs. If erasure has been
completed on all the erase blocks, clear the SWE1 bit in FLMCR1. If there are any unerased
blocks, make a 1 bit setting for the flash memory area to be erased, and repeat the erase/erase-
verify sequence as before.
Rev. 5.00 Jan 10, 2006 page 656 of 1042
REJ09B0275-0500
be erased to all 0) is not necessary before starting the erase procedure.
Erase Mode
Erase-Verify Mode