HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 928

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Appendix B Internal I/O Register
BCRA—Break Control Register A
BCRB—Break Control Register B
Rev. 5.00 Jan 10, 2006 page 902 of 1042
REJ09B0275-0500
Notes: The bit configuration of BCRB is the same as that of BCRA, except that BCRB performs break control
Bit
Initial value
Read/Write
for channel B.
* Can only be written with 0 for flag clearing.
:
:
:
R/(W)*
CMFA
Condition match flag
7
0
0 [Clearing condition]
1
When 0 is written to CMFA after reading CMFA = 1
[Setting condition]
When a condition set for channel A is satisfied
CDA
R/W
CPU cycle/DTC cycle select A
0 PC break is performed when CPU is bus master
1
6
0
PC break is performed when CPU or DTC is bus master
BAMRA2
Break address mask register
R/W
0
1
5
0
0
1
0
1
0
1
0
1
0
1
0
1
BAMRA1
Break condition select
All BARA bits are unmasked and included in break
conditions
BAA0 (lowest bit) is masked, and not included in break
conditions
BAA1–0 (lower 2 bits) are masked, and not included
in break conditions
BAA2–0 (lower 3 bits) are masked, and not included
in break conditions
BAA3–0 (lower 4 bits) are masked, and not included
in break conditions
BAA7–0 (lower 8 bits) are masked, and not included
in break conditions
BAA11–0 (lower 12 bits) are masked, and not included
in break conditions
BAA15–0 (lower 16 bits) are masked, and not included
in break conditions
R/W
0
1
4
0
0 Instruction fetch is used as break condition
1
0
1
H'FE08
H'FE09
Data read cycle is used as break condition
Data write cycle is used as break condition
Data read/write cycle is used as break condition
BAMRA0
R/W
3
0
Break interrupt enable
0 PC break interrupts are disabled
1
CSELA1
PC break interrupts are enabled
R/W
2
0
CSELA0
R/W
1
0
BIEA
R/W
0
0
PBC
PBC