HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 267

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. In
modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the SCI’s
SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS
input pull-up for that pin.
In mode 7, if a pin is in the input state in accordance with the settings in the SCI’s SCMR, SMR,
and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up
for that pin.
PAPCR is initialized to H'0 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode.
Port A Open Drain Control Register (PAODR)
Note:
PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each
port A pin (PA5 to PA0).
Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.
When pins are not address outputs in accordance with the setting of bits AE3 to AE0 in PFCR,
setting a PAODR bit makes the corresponding port A pin an NMOS open-drain output, while
clearing the bit to 0 makes the pin a CMOS output.
PAODR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode.
Bit
Initial value :
R/W
* In the H8S/2626 Group bits 5 and 4 are reserved, and will return an undefined value if
read.
:
:
Undefined Undefined
—
—
7
—
—
6
PA5ODR * PA4ODR * PA3ODR
R/W
5
0
R/W
4
0
Rev. 5.00 Jan 10, 2006 page 241 of 1042
R/W
3
0
PA2ODR
R/W
2
0
Section 9 I/O Ports
PA1ODR
REJ09B0275-0500
R/W
1
0
PA0ODR
R/W
0
0