HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 15

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.6
7.7
7.8
7.9
7.10 Resets and the Bus Controller ........................................................................................... 182
Section 8 Data Transfer Controller (DTC)
8.1
8.2
8.3
Idle Cycle .......................................................................................................................... 174
7.6.1
7.6.2
Write Data Buffer Function .............................................................................................. 177
Bus Release....................................................................................................................... 178
7.8.1
7.8.2
7.8.3
7.8.4
7.8.5
Bus Arbitration.................................................................................................................. 181
7.9.1
7.9.2
7.9.3
Overview........................................................................................................................... 183
8.1.1
8.1.2
8.1.3
Register Descriptions ........................................................................................................ 186
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
Operation .......................................................................................................................... 193
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
Operation ............................................................................................................. 174
Pin States in Idle Cycle ........................................................................................ 176
Overview.............................................................................................................. 178
Operation ............................................................................................................. 178
Pin States in External Bus Released State............................................................ 179
Transition Timing ................................................................................................ 180
Usage Note........................................................................................................... 181
Overview.............................................................................................................. 181
Operation ............................................................................................................. 181
Bus Transfer Timing ............................................................................................ 182
Features................................................................................................................ 183
Block Diagram ..................................................................................................... 184
Register Configuration......................................................................................... 185
DTC Mode Register A (MRA) ............................................................................ 186
DTC Mode Register B (MRB)............................................................................. 188
DTC Source Address Register (SAR).................................................................. 189
DTC Destination Address Register (DAR).......................................................... 189
DTC Transfer Count Register A (CRA) .............................................................. 190
DTC Transfer Count Register B (CRB)............................................................... 190
DTC Enable Registers (DTCER) ......................................................................... 191
DTC Vector Register (DTVECR)........................................................................ 192
Module Stop Control Register A (MSTPCRA) ................................................... 193
Overview.............................................................................................................. 193
Activation Sources ............................................................................................... 195
DTC Vector Table................................................................................................ 197
Location of Register Information in Address Space ............................................ 200
Normal Mode....................................................................................................... 201
Repeat Mode ........................................................................................................ 202
Block Transfer Mode ........................................................................................... 203
Chain Transfer ..................................................................................................... 205
Operation Timing................................................................................................. 206
................................................................... 183
Rev. 5.00 Jan 10, 2006 page xiii of xxiv