HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 681

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first
Reprogram Data Computation Table
Original Data
Note: 6. Programming Time
Number of Writes
(D)
0
0
1
1
2. Verify data is read in 16-bit (word) units.
3. Even bits for which programming has been completed in the 128-byte programming
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data,
5. A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See note *6 for details of the pulse widths.
N1+N2–2
N1+N2–1
Write pulse application subroutine
address written to must be H'00 or H'80. A 128-byte data transfer
must be performed even if writing fewer than 128 bytes; in this case,
H'FF data must be written to the extra addresses.
loop will be subject to programming again if they fail the subsequent verify operation.
and a 128-byte area for storing additional-programming data must be provided in RAM.
The reprogram and additional-programming data contents are modified as programming proceeds.
When writing of additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
tspsu:
N1+N2
N1–1
N1+1
N1+2
N1+3
tcp:
Wait (z0) µs or (z1) µs or (z2) µs
N1
1
2
·
·
·
·
·
·
Clear PSU1 bit in FLMCR1
Verify Data
Set PSU1 bit in FLMCR1
Sub-Routine Write Pulse
tsp10 or tsp30 or tsp200:
data storage area (128 bytes)
Clear P1 bit in FLMCR1
Set P1 bit in FLMCR1
Reprogram data storage
Additional-programming
Program data storage
(V)
0
1
0
1
area (128 bytes)
area (128 bytes)
Disable WDT
Enable WDT
Wait ( ) µs
Wait ( ) µs
Wait (y) µs
End Sub
Programming
RAM
Reprogram Data
P1 Bit Set Time (µs)
z0
z0
z0
z0
z2
z2
z2
z2
z2
z2
·
·
·
·
·
·
(X)
1
0
1
1
Programming
Additional
Figure 19.11 Program/Program-Verify Flowchart
*
5
z1
z1
z1
z1
—
—
—
—
—
—
·
·
·
·
·
·
Programming complete
Programming is incomplete:
reprogramming should be performed
Left in the erased state
Comments
Increment address
Successively write 128-byte data from additional-
Transfer reprogram data to reprogram data area
programming data area in RAM to flash memory
Additional-Programming Data Computation Table
Reprogram Data
Store 128 bytes of program data in program
Additional-programming data computation
NG
Transfer additional-programming data to
Successively write 128-byte reprogram
tcswe:
tcswe:
tsswe:
tspv:
tspur:
H'FF dummy write to verify address
tcpv:
data area and reprogram data area
Additional programming subroutine
additional-programming data area
Write pulse application subroutine
(X')
0
0
1
1
Reprogram data computation
Clear SWE1 bit in FLMCR1
Set SWE1 bit in FLMCR1
Clear PV1 bit in FLMCR1
Set PV1 bit in FLMCR1
Start of programming
verification completed?
data to flash memory
End of programming
Read verify data
Program data =
Wait ( 0) µs
128-byte data
Wait ( 1) µs
verify data?
Wait ( ) µs
Wait ( ) µs
Wait ( ) µs
OK
OK
Verify Data
N1
N1
START
m = 0 ?
m = 0
n = 1
(V)
0
1
0
1
Rev. 5.00 Jan 10, 2006 page 655 of 1042
n ?
n ?
Sub-Routine-Call
Sub-Routine-Call
OK
OK
Additional-Programming
NG
NG
NG
NG
Data (X)
0
1
1
1
Section 19 ROM (Preliminary)
*
*
*
*
*
*
4
1
5
2
4
3
Programming must be executed in the erased state.
Do not perform additional programming on addresses
that have already been programmed.
*
*
4
1
tcswe:
m = 1
Additional programming should be performed
Additional programming should not be performed
Additional programming should not be performed
Additional programming should not be performed
Clear SWE1 bit in FLMCR1
Programming failure
n
Wait ( 1) µs
(N1 + N2) ?
REJ09B0275-0500
OK
Comments
NG
n
n + 1